NDLI: Performance evaluation of hardware models of Advanced Encryption Standard (AES) algorithm

Content Provider	IEEE Xplore Digital Library
Author	Yenuguvanilanka, J. Elkeelany, O.
Copyright Year	2008
Description	Author affiliation: Tennessee Technol. Univ., Cookeville (Yenuguvanilanka, J.; Elkeelany, O.)
Abstract	In today's world most of the communication is done using electronic media. Data Security plays a vital role in such communication. Hence, there is a need to protect data from malicious attacks. Advanced Encryption Standard (AES), also known as Rijndael, is an encryption standard used for securing information. AES is a block cipher algorithm that has been analyzed extensively and is now used widely. The hardware implementation of AES algorithm is faster and more secure than software implementation. There are different hardware models to implement the Rijndael Encryption core. This paper addresses the performance of Rijndael AES Encryption algorithm of key length 128 bits. Two hardware models based on HDL and IP core are used to evaluate the performance of the algorithm. The encryption time and also the performance metrics such as size, speed and memory utilization are evaluated, using these models. Results are compared to a reference model and have shown an increase in the throughput per slice measure.
Starting Page	222
Ending Page	225
File Size	348129
Page Count	4
File Format	PDF
ISBN	9781424418831
DOI	10.1109/SECON.2008.4494289
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Cryptography NIST Algorithm design and analysis Data security Pipeline processing Software algorithms Computer architecture Output feedback Iterative algorithms
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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