NDLI: Comparison between bulk and SOI MOSFETs for sub-100nm mixed mode applications

Content Provider	IEEE Xplore Digital Library
Author	Suryagandh, S.S. Garg, M. Woo, J.C.S.
Copyright Year	2003
Description	Author affiliation: Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA (Suryagandh, S.S.; Garg, M.; Woo, J.C.S.)
Abstract	This paper presents a systematic and quantitative comparison between the analog characteristics of bulk and SOI technology. An analog performance metric of intrinsic gain, f/sub T/ and g/sub m//I/sub ds/ ratio is considered. The impact of device scaling on this performance metric has been analyzed. It is shown that, even for the frequencies in the range of GHz (where the AC kink effect is totally suppressed), the analog performance of SOI devices is inferior to that of the bulk devices due to capacitive drain-to-body coupling. Based on our study, we propose that gate-workfunction engineering is essential in FDSOI devices for improving analog performance at a threshold voltage compatible with the bulk technology.
Sponsorship	IEEE EDS Infineon Technol. ATMEL Tower Semiconductor Ltd
Starting Page	423
Ending Page	426
File Size	323790
Page Count	4
File Format	PDF
ISBN	0780379993
DOI	10.1109/ESSDERC.2003.1256904
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-09-16
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Doping Silicon Performance gain Radio frequency Digital circuits Isolation technology Guidelines Measurement Threshold voltage
Content Type	Text
Resource Type	Article

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Design considerations of Sub-100nm Dual Material Gate Fully Depleted Silicon On Insulator (DMG-FD-SOI)

Study of RF Performance for Graded-Channel SOI MOSFETs

High performance, sub-50nm MOSFETS for mixed signal applications

Comparative Performance Evaluation of Bulk and FD-SOI MOSFETs Using TCAD

Analog/RF performance of sub-100 nm SOI MOSFETs with non-classical gate-source/drain underlap channel design

Electrical characteristics comparison between partially-depleted SOI and n-MOS devices investigation using Silvaco

Sub-micron fully depleted lateral asymmetric channel SOI MOSFETs for analog and mixed mode applications

Investigation of the Threshold Voltage Difference between Partially-Depleted SOI and bulk CMOS transistors

Periodic Transconductance Oscillations in Sub-100nm MOSFETs

Comparison between bulk and SOI MOSFETs for sub-100nm mixed mode applications

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