NDLI: A 0.7–1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection

Content Provider	IEEE Xplore Digital Library
Author	van Liempd, B. Ariumi, S. Martens, E. Shih-Hung Chen Wambacq, P. Craninckx, J.
Copyright Year	2015
Description	Author affiliation: imec, Leuven, Belgium (van Liempd, B.; Martens, E.; Shih-Hung Chen; Craninckx, J.) \|\| Dept. of Electron. & Inf. (ETRO), Vrije Univ. Brussel, Brussels, Belgium (Wambacq, P.)
Abstract	IM3-cancellation is a popular technique in LNAs to achieve very high linearity, but is also very sensitive to the exact device (bias) operating point. A 0.7-1.15GHz complementary common-gate LNA in 0.18μm silicon-on-insulator CMOS is presented that achieves good out-of-band (OOB) linearity without IM3-cancellation. Measurements of the $0.9mm^{2}$ prototype show a gain of >7dB, an NF of <;2.3dB, more than +15dBm OOB-IIP3 and over 0dBm B1dB. Compared to other work, this LNA has a similar or better linearity at only 10mW. The LNA uses a nominal supply of 2.5V, but was tested up to 3.7V and showed no significant degradation of its linearity for ±400mV supply variations. A power clamp, designed to enable testing at higher core supply voltage, withstands a >2.6kV HBM discharge, while the overall circuit is protected for >1kV HBM discharges.
Starting Page	164
Ending Page	167
File Size	496143
Page Count	4
File Format	PDF
ISBN	9781467374705
ISSN	19308833
e-ISBN	9781467374729
DOI	10.1109/ESSCIRC.2015.7313854
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-14
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Linearity Electrostatic discharges CMOS integrated circuits Clamps Noise measurement Discharges (electric) Radio frequency electrostatic discharges Low-noise amplifiers silicon-on-insulator CMOS nonlinear distortion
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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