NDLI: A single–chip speech recognition system with embedded flash memory and configurable data path

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Table of contents

Nanoscale system design challenges: Business as usual?

High-speed A/D converters for telecom applications

How fast can you go? efficient design methods for RF transceivers at 5 GHz and beyond

The art and science of integrated systems design

Microelectronics meets biology: Challenges and opportunities for functional integration in lab-on-a-chip

Future trend of microprocessor design

Power aware wireless microsensor systems

Prospects for single molecule information devices

Ultra low-power multimedia processor for mobile multimedia applications

A heterogeneous multi-core platform for low power signal processing in systems-on-chip

Implementation of a 256-bit wideword processor for the data-intensive architecture (DIVA) processing-in-memory (PIM) chip

An approach for a flexilble interface platform

A high-stability, ultra-low-power quartz differential oscillator circuit for demanding radio applications

18 GHz and 7 GHz superharmonic injection-locked dividers in 0.25µm CMOS technology

A 15mW fully integrated I/Q synthesizer for bluetooth in 0.18µm CMOS

A single-chip 10,000 frames/s CMOS tracking image sensor for complex targets

A smart position sensor with row parallel position detection for high speed 3-D measurement

Smart sensor architecture for real-time high-resolution range finding

Reliable handling of fempto-ampere currents in standard CMOS

A CMOS adaptive interference reduction system for nerve cuff recordings

A new correlated double sampling (CDS) technique for low voltage design environment in advanced CMOS technology

The millipede, a very dense, highly parallel scanning-probe data-storage system

Planar 1T-cell DRAM with MOS storage capacitors in a 130nm logic technology for high density microprocessors caches

A 0.13-µm CMOS NOR flash memory experimental chip for 4-b/cell digital storage

Design of a 3D fully-depleted SOI computational RAM

A $6.7-fF/µm^{2}bias-independent$ gate capacitor (BIGCAP) with standard CMOS process and its application to the loop filter of a differential PLL

Linear controlled temperature independent varactor circuitry

A 2.6 GHz low phase-noise VCO monolithically integrated with high Q MEMS inductors

A 300µmW 1.9GHz CMOS oscillator utilizing micromachined resonators

A 24GHz CMOS front-end

28 GHz active I/Q mixer with integrated QVCO in SiGe bipolar technology

A 5GHz BiCMOS RFIC front end for IEEE 802.11a/hiperLAN wireless LAN

Transceiver front-end with integrated TX/RX commutator for bluetooth applications

A 150/400/800/1900 MHz low noise Cartesian feedback IC with programmable loop bandwidth

A 1.2V, 200µW rail-to-rail Op Amp with 90dB THD using replica gain enhancement

Constant–grail–to–rail input/output Op–Amp for video applications

250 MHz CMOS rail–to–rail IO OpAmp: Structural design approach

A 250+dB open loop gain feedforward compensated high precision operational amplifier

A low–voltage fully balanced OTA with common mode feedforward and inherent common mode feedback detector

Fast signal propagation for point to point on–chip long interconnects using current sensing

Wire self–heating in supply lines on bulk–CMOS ICs

A dual–rail PLA with 2–input logic cells

A slew rate controlled output driver using PLL as compensation circuit

Energy–delay tradeoffs in combinational logic using gate sizing and supply voltage optimization

A low voltage fully–integrated 0.18um CMOS power amplifier for 5GHz WLAN

A fully integrated class 1 bluetooth 0.25µm CMOS PA

A monolithic 2.45GHz power amplifier in SiGe–bipolar with 0.4W output power and 53% PAE at 2V

A 15 Gb/s 4:1 parallel–to–serial data multiplexer in 0.12µm CMOS

A low–power 20–Gb/s CMOS 2:1 multiplexer/driver

A CMOS 7–Gb/s power–efficient 4–PAM transmitter

A 4–Gb/s clock and data recovery circuit using four–phase 1/8–rate clock

Analog timing recovery for noise–predictive DFE

A 0.5V, 1µW successive approximation ADC

A 10–bit charge–transfer amplifier–based A/D converter with 400–µW/MSPS dynamic power dissipation

An ultra–low power ADC for distributed sensor networks

A low–power 16–channel AD converter and digital processor ASIC

A multichannel, pipeline analog–to–digital converter for an integrated 3–D ultrasound imaging system

A novel sub–1 V high speed circuit design technique in partially depleted SOI–CMOS technology with ultra low–leakage power

Sense–amplifierless DCSL: A circuit style tolerant to floating body effects in PD/SOI

An accurate estimation model for subthreshold CMOS SOI logic

A versatile 1.75mW CMOS continuous–time delta–sigma ADC with 75dB dynamic range for wireless applications

A 5mW, 100kHz bandwidth, current–mode continuous–time Σ–Δ modulator with 84 dB dynamic range

A continuous–time sigma–delta modulator with reduced jitter sensitivity

Modeling and experimental verification of substrate noise generation in a 220Kgates WLAN system–on–chip with multiple supplies

Dynamic hot spot temperature sensing in smart power switches

Reducing substrate coupling in 10 to 40 Gbit/s high–gain broadband amplifiers

Multi–pole bandwidth enhancement technique for trans-impedance amplifiers

A 270MHz, 1 V, low–distortion variable gain amplifier in 0.35µm CMOS process

A 15mW 280MHz 80dB gain CMOS limiting/logarithmic amplifier with active cascode gain–enhancement

High–performance, low–power, and leakage–tolerance challenges for sub–70nm microprocessor circuits

Adaptive PRML core development for SoC CD/DVD multi controller IC

A single–chip speech recognition system with embedded flash memory and configurable data path

A highly flexible, module–based SoC–approach for VoIP–applications

A 1.3dB NF CMOS LNA for GPS with 3kV HBM ESD–protection

A 5.2GHz LNA in 0.35µm CMOS utilizing inter–stage series resonance and optimizing the substrate resistance

A 2.7V, 1.8GHz, $4^{th}order$ tunable LC bandpass filter with ± 0.25dB passband ripple

A packaged 2.4 GHz LNA in a 0.15µm CMOS process with 2kV HBM ESD protection

A tuned, inductorless, recursive filter LNA in CMOS

Fully–integrated active–quenching circuit for single–photon detection

CMOS active differential imaging device with single in–pixel analog memory

A switched–capacitor variable gain amplifier for CCD image sensor interface system

VISoc: A smart camera SoC

A CMOS analog parallel array processor chip with programmable dynamics for early vision tasks

A noise–shaped switched–capacitor DC–DC voltage regulator

A fast response adaptive DC–DC switching converter using on–chip dual–loop one–cycle control

Low–drift bandgap voltage references

Precision and robust CMOS voltage reference based on the work function difference of poly Si gate

A new voltage reference topology based on subthreshold MOSFETs

Current mirror evaluation logic: A new circuit style for high fan–in dynamic gates

A low power symmetrically pulsed dual edge–triggered flip–flop

A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards

Self–precharging flip–flop (SPFF): A new level converting flip–flop

A self–controllable–voltage–level (SVL) circuit for low– power, high–speed CMOS circuits

A sub–psec jitter PLL for clock generation in 0.12µm digital CMOS

A 10–Gb/s clock recovery circuit with linear phase detector and coupled two–stage ring oscillator

Low–voltage CMOS charge–pump PLL architecture for low jitter operation

A 100MHz, 8mW ROM–less quadrature direct digital frequency synthesizer

A $35–mW–3.6mm^{2}fully$ integrated 0.18µm CMOS GPS radio

A SiGe RF front–end with on–chip VCO for a GPS receiver

Fully integrated zero IF transceiver for GPRS/GSM/DCS/PCS application

A direct conversion CMOS receiver front-end with on-chip LO for UMTS

A highly integrated Si/SiGe BiCMOS upconverter RFIC For 3G WCDMA handset applications

A 1–GS/s 2.7–V track–and–hold amplifier with 10–b resolution at Nyquist in SiGe BiCMOS

A 1.8–V, 6–bit, 1.3–GHz CMOS flash ADC in 0.25 µm CMOS

A 14mW 10–bit 20–Msample/s ADC in 0.18um CMOS with 61MHz–input

An 11b 70 MHz 1.2 $mm^{2}49mW$ 0.18 um CMOS ADC with on–chip current/voltage references

A 12b 80MSps pipelined ADC core with 190mW consumption from 3V in 0.18µm digital CMOS

A 10–bit, 100–MHz CMOS linear interpolation DAC

A pipelined D/A converter with an improved driving scheme for DMT–signals

Current mode deglitcher for current–steering DACs

A 0.7dB insertion loss CMOS–SOI antenna switch with more than 50dB isolation over the 2.5 to 5GHz band

MEMS variable capacitor versus MOS variable capacitor for a 5GHz voltage controlled oscillator

Influence of the MOS varactor gate doping on the performance of a 2.7GHz–4GHz LC–VCO in standard digital 0.12µm CMOS technology

Generic and intelligent CMOS 155 Mb/s burst mode laser driver chip design and performance

A monolithic 4×4 TIA, crosspoint switch and laser driver IC with very high programming speed

A 20 Mbit/s integrated photoreceiver with digital outputs in 0.6µm CMOS technology

A high–speed monolithic amplifier for CRT drivers in SOI

An integrated 200W class D audio amplifier

A novel coding topology for digital class–D audio power amplifiers with very low pulse–repetition rate

A high speed Reed–Solomon decoder chip using inversionless decomposed architecture for Euclidean algorithm

500 Mb/s soft output Viterbi decoder

Direct digital frequency synthesizers using first–order polynomial Chebyshev approximation

Real time implementation on FPGA of an OFDM based wireless LAN modem extended with adaptive loading

Microstrip coupled VCOs for 40–GHz and 43–GHz OC–768 optical transmission

A low–phase–noise 5GHz quadrature CMOS VCO using common–mode inductive coupling

An integrated 10/5GHz injection–locked quadrature LC VCO in a 0.18µm digital CMOS process

A wide–tuning range transfomer–based RF CMOS oscillator

Fully integrated 5GHz CMOS VCOs with on chip low frequency feedback circuit for 1/f induced phase noise suppression

Driving the DSL highway : High speed, high density, low power, low cost

A DMT–based VDSL receiver front–end design in 0.35µm BiCMOS

A frequency division duplexing DMT–based modem tranceiver for VDSL

A 2V low–power CMOS 125Mbaud repeater architecture for UTP5 cables

A 10.7MHz self–calibrated SC multibit 2nd–order bandpass Σ–Δ modulator

A second order sigma delta modulator using semi–uniform quantizer with 81dB dynamic range at 32x OSR

A 14–bit delta–sigma modulator for ADSL–CO applications in 0.18µm CMOS

Ultra low–voltage MOSFET–only switched–Opamp ΣΔ modulators using depletion–mode MOS–capacitors

A 10MHz IF digitizer using a novel quadrant based swapping scheme for I, Q mismatch elimination that achieves an equivalent 65dB image rejection ratio

Design of an on–chip random number generator using metastability

Expandable high throughput vector based access memory architecture

Globally updated mesochronous design style (GUM–design–style)

A clock tuning circuit for system–on–chip

Low jitter design of a 0.35µm–CMOS frequency divider operating up to 3GHz

92 GHz cut–off frequency InP double channel HEMT based coplanar distributed amplifier for 40 Gbit/s applications and beyond

RF circuit implications of a low–current linearity "Sweet spot" in MOSFETs

CMOS sensor array with cell–level analog–to–digital conversion for local probe date storage

A mixed–signal hall sensor IC with direction detection

A 80dB–SNR ±1g fully–integrated biaxial linear accelerometer in a standard 0.5µm CMOS technology for high–sensitivity applications

A low noise switched–capacitor interface circuit for sub–micro gravity resolution micromachined accelerometers

ΣΔ capacitive interface for a vertically-driven X&Y-axis rate gyroscope

A 2V, 80–200MHz fourth–order continuous–time linear phase filter with automatic frequency tuning

A 1.5 V 75 dB–dynamic range $3^{rd}–order$ G–C filter integrated in a 0.18 µm standard digital CMOS process

A multiple–shape channel selection filter for multimode zero–IF receiver using capacitor over active device implementation

Design considerations for large dynamic range MOSFET–C filters for direct conversion receivers

A Gm–C filter using multiple–output linearized transconductors

New standby–current reduction technique for deep sub–micron VLSI CMOS circuits: Smart series switch

A high–speed functional memory with a capability of hamming–distance–based data search by dynamic threshold logic circuits

Circuit design with metallic single–electron tunneling junctions

Domino logic with dynamic body biased keeper

Zigzag super cut–off CMOS (ZSCCMOS) scheme with self–saturated virtual power lines for subthreshold–leakage–suppressed sub–1–V–VLSI's

Very fast EEPROM erasing study

A novel multi–bit parallel ΔΣ FM–to–digital converter with 24–bit resolution

A high–speed, high–bandwidth, low resolution flash ADC for radio astronomy applications

A mixed–mode array processor with polynomial–type couplings

A differential bipolar stray–insensitive quasi–passive pipelined digital–to–analog converter with 17.664 MSps sample rate and -85dB THD

An image region extraction LSI based on a merged/mixed–signal nonlinear oscillator network circuit

A CMOS time to digital converter for space science instruments

A 10 bit, low power, digitally auto–zeroed CMOS analogue to digital converter core for the NASA TRIO smart sensor system on a chip

A 5.9mW 6.5GMACS CID/DRAM array processor

A continuous time pattern recognition retina

High speed digital CMOS 2D optical position sensitive detector

Very low power high temperature stability bandgap reference voltage

A class AB CMOS operational amplifier for application as rail–to–rail high current drive output buffer

1.5–V high–drive second generation current conveyor

Low voltage class–AB output stages for CMOS Op–Amps

Efficiency analysis of a high frequency buck converter for on–chip integration with a dual–Vmicroprocessor

A CMOS analog FIR filter with low phase distortion

A CMOS current amplifier for very weak current operations

A new CMOS 4Q–multiplier using linear and saturation regions complementally

Comparison of programmable FIR filter architectures for low power

Optimising broadband signal transfer across long on–chip interconnect

The address translation unit of the data–intensive architecture (DIVA) system

Fast algorithm for clock grid simulation

A low distortion wide band CMOS direct digital RF amplitude modulator

A novel 1–Gbps clock and data recovery architecture using synchronous oscillator in CMOS VLSI technology

Design considerations and experimental verification of a self oscillating line driver in .35µm CMOS

A 1.35Gbps decision feedback equalizing receiver for the SSTL SDRAM interface with 2X oversampling phase detector for skew compensation between clock and data

A 3–V area–efficient wideband low–noise converter for multi–band multi–standard low–IF wireless receiver

1 volt CMOS bluetooth front–end

A CMOS fully integrated 1 GHz and 2 GHz dual band VCO with a voltage controlled inductor

A fractional–N frequency synthesizer with a 3–bit $4^{th}order$ Σ–Δ modulator

A 5–GHz band I/Q clock generator using a self–calibration technique

Phase noise improvement of deep submicron low–voltage VCO

A 2GHz, 17% tuning range quadrature CMOS VCO with high figure–of–merit and 0.6° phase error

A cost–effective multi–band LC oscillator for low–IF FM radio receivers

A high sensitivity static 2:1 frequency divider up to 27GHz in 120nm CMOS

High–performance and low–voltage divider circuits fabricated in SiGe:C HBT technology

A 900 MHz, 2.7 V highly linear driver amplifier using 0.5 µm Si BiCMOS

LNA design for a fully integrated CMOS single chip UMTS transceiver

Fully integrated 2-stage power amplifier module for 2.4 GHz ISM-band applications realised on $1mm^{2}digital$ CMOS technology

A CMOS programmable divider for RF multistandard frequency synthesizers

Proceedings of the 27th European Solid-State Circuits Conference

Proceedings of the 26th European Solid-State Circuits Conference

Proceedings of the 25th European Solid-State Circuits Conference

Proceedings of the 24th European Solid-State Circuits Conference

Proceedings of the 23rd European Solid-State Circuits Conference

ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference

ESSCIRC '95: Twenty-first European Solid-State Circuits Conference

ESSCIRC '94: Twientieth European Solid-State Circuits Conference

ESSCIRC '93: Nineteenth European Solid-State Circuits Conference

ESSCIRC '92: Eighteenth European Solid-State Circuits conference

ESSCIRC '91: Proceedings - Seventeenth European Solid-State Circuits Conference

ESSCIRC '90: Sixteenth European Solid-State Circuits Conference

ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference

ESSCIRC '88: Fourteenth European Solid-State Circuits Conference

ESSCIRC '87: 13th European Solid-State Circuits Conference

ESSCIRC '86: Twelfth European Solid-State Circuits Conference

ESSCIRC '85: 11th European Solid-State Circuits Conference

ESSCIRC '84: Tenth European Solid-State Circuits Conference

ESSCIRC '83: Ninth European Solid-State Circuits Conference

ESSCIRC '82: Eighth European Solid-State Circuits Conference

ESSCIRC '81: 7th European Solid State Circuits Conference

ESSCIRC 80: 6th European Solid State Circuits Conference

Fifth European Solid State Circuits Conference - ESSCIRC 79

ESSCIRC 78: 4th European Solid State Circuits Conference - Digest of Technical Papers

ESSCIRC '77: 3rd European Solid State Circuits Conference

ESSCIRC 76: 2nd European Solid State Circuits Conference

1975 First European Solid State Circuits Conference (ESSCIRC)

A single–chip speech recognition system with embedded flash memory and configurable data path

Content Provider	IEEE Xplore Digital Library
Author	Cali, L. Lertora, F. Borgatti, M.
Copyright Year	2002
Description	Author affiliation: STMicroelectronics, Agrate Brianza, Italy (Cali, L.)
Abstract	The design of a single-chip, processor-based system with embedded built-in speech recognition capabilities is presented. The proposed system-on-chip is intended to be used for the implementation of autonomous embedded systems featuring voice control capabilities and command-oriented user interface. To allow a good flexibility of the recognition system and to achieve a single-chip system implementation, the main processing functionalities have been organized as co-processors and integrated around a 32-bit processor and a 2Mb embedded flash memory. The architecture of the system that features a recognition engine with a configurable data path is discussed. The silicon area required by the system is 25 $mm^{2}in$ a 0.18µm CMOS embedded flash technology.
Starting Page	327
Ending Page	330
File Size	302332
Page Count	4
File Format	PDF
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-24
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Non IEEE
Subject Keyword	Speech recognition Flash memory CMOS technology System-on-a-chip Embedded system Control systems User interfaces Coprocessors Memory architecture Engines
Content Type	Text
Resource Type	Article

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