NDLI: A low–power 16–channel AD converter and digital processor ASIC

Content Provider	IEEE Xplore Digital Library
Author	Subiela, D. Engels, S. Dugoujon, L. Esteve-Bosch, R. Mota, B. Musa, L. Jimenez-de-Parga, A.
Copyright Year	2002
Description	Author affiliation: STMicroelectronics (Subiela, D.)
Abstract	The extreme particle density in the detectors for high-energy physics experiments set new demands on the readout electronics in terms of resolution, density and power consumption. These requirements are beyond the present capability of commercial-off-the-shelf components and call for ASICs that embed in a single chip the circuits to digitise, process, compress and store the information of a high number of channels. In this paper we present an ASIC that responds to these needs, including in a single chip 16 low-power 10-bit 25-MSPS A/D converters, a data processor and 800-Kbit of memory. The chip, which is implemented in a 0.25 µm CMOS technology, has an area of $64mm^{2}and$ a power consumption of 320mW when the 16 channels are running at 10MHz rate. The measurements show a resolution better than 9.5 ENOB on all channels and a channel-to-channel crosstalk below -65dB. The techniques adopted in the front-end and back-end design of the circuit, to limit the impact of the digital noise on the ADC performance and the channel-to-channel crosstalk, are also presented.
Starting Page	259
Ending Page	262
File Size	303825
Page Count	4
File Format	PDF
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-24
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Non IEEE
Subject Keyword	Application specific integrated circuits Detectors Crosstalk Physics Readout electronics Energy consumption CMOS technology Large Hadron Collider Pulse amplifiers Semiconductor device measurement
Content Type	Text
Resource Type	Article

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