NDLI: A 0.1e- vertical FPN 4.7e- read noise 71dB DR CMOS image sensor with 13b column-parallel single-ended cyclic ADCs

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2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

2012 IEEE International Solid-State Circuits Conference

2011 IEEE International Solid-State Circuits Conference

2010 IEEE International Solid-State Circuits Conference - (ISSCC)

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

Table of contents

Session 1 Overview Plenary session

Leaner and greener: Adapting to a changing climate of innovation

Adaptive circuits for the 0.5-V nanoscale CMOS era

The new era of scaling in an SoC world

Kids today! Engineers tomorrow?

Session 2 Overview Imagers

A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor

A gamma, x-ray and high energy proton radiation-tolerant CIS for space applications

A 4-channel 20-to300 Mpixel/s analog front-end with sampled thermal noise below kT/C for digital SLR cameras

A 1/2.5-inch 8Mpixel CMOS image sensor with a staggered shared-pixel architecture and an FD-boost operation

An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applications

PDF not available [Paper withdrawn by author]

A charge-multiplication CMOS image sensor suitable for low-light-level imaging

A dual-conversion-gain video sensor with dewarping and overlay on a single chip

Session 3 Overview Microprocessor technologies

A 45nm 8-core enterprise Xeon® processor

A family of 45nm IA processors

A chip-stacked memory for on-chip SRAM-rich SoCs and processors

Dynamic frequency-switching clock system on a quad-core Itanium® processor

Secure AES engine with a local switched-capacitor current equalizer

A 4Gb/s/ch 356fJ/b 10mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm CMOS

Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring

Over one million TPCC with a 45nm 6-core Xeon® CPU

Session 4 Overview High-speed data converters

A 12b 2.9GS/s DAC with IM3 ≪−60dBc beyond 1GHz in 65nm CMOS

A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS

A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency

A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS

A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization

A 10b 500MHz 55mW CMOS ADC

A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC

Session 5 Overview Potpourri: PLL, optical, DSL

A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90nm CMOS

Subharmonically injection-locked PLLs for ultra-low-noise clock generation

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications

0.9mW 7GHz and 1.6mW 60GHz frequency dividers with locking-range enhancement in 0.13µm CMOS

A 5.4mW $0.0035mm^{2}$ 0.48ps-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS

A 14mW 5Gb/s CMOS TIA with gain-reuse regulated cascode compensation for parallel optical interconnects

A 4Gb/s current-mode optical transceiver in 0.18µm CMOS

Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit

CMOS optical 4-PAM VCSEL driver with modal-dispersion equalizer for 10Gb/s 500m MMF transmission

A VDSL2 CPE AFE in 0.15µm CMOS with integrated line driver

Session 6 Overview Cellular and tuner

An integrated closed-loop polar transmitter with saturation prevention and low-IF receiver for quad-band GPRS/EDGE

A SAW-less multiband WEDGE receiver

Single-chip multiband WCDMA/HSDPA/HSUPA/EGPRS transceiver with diversity receiver and 3G DigRF interface without SAW filters in transmitter / 3G receiver paths

Single-chip RF CMOS UMTS/EGSM transceiver with integrated receive diversity and GPS

A 45nm low-power SAW-less WCDMA transmit modulator using direct quadrature voltage modulation

An embedded 65nm CMOS low-IF 48MHz-to-1GHz dual tuner for DOCSIS 3.0

A 1.2V 67mW $4mm^{2}$ mobile ISDB-T tuner in 0.13µm CMOS

Session 7 Overview DRAM

1.2V 1.6Gb/s 56nm $6F^{2}$ 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture

8Gb 3D DDR3 DRAM using through-silicon-via technology

A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application

75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques

Single-ended transceiver design techniques for 5.33Gb/s graphics applications

A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

Low-V small-offset gated preamplifier for sub-1V gigabit DRAM arrays

Session 8 Overview Multimedia processors

An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply

A versatile recognition processor employing Haar-like feature and cascaded classifier

A 201.4GOPS 496mW real-time multi-object recognition processor with bio-inspired neural perception engine

A multi-format Blu-ray player SoC in 90nm CMOS

A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications

A 45nm single-chip application-and-baseband processor using an intermittent operation technique

A 342mW mobile application processor with full-HD multi-standard video codec

Session 9 Overview Data converter techniques

A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic distortion correction

A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumps

A 12b 50MS/s fully differential zero-crossing-based ADC without CMFB

A 9b 14µW $0.06mm^{2}$ PPM ADC in 90nm digital CMOS

A 0.13µm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based integrator and quantizer

A 1.2V 2MHz BW $0.084mm^{2}$ CT ΔΣ ADC with −97.7dBc THD and 80dB DR using low-latency DEM

A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element

A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS

Session 10 Overview Multi-Gb/s serial links and building blocks

A Scalable 3.6-to-5.2mW 5-to-10Gb/s 4-tap DFE in 32nm CMOS

A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS

A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate

10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution $1^{st}-order$ ΔΣ modulator

A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control

A 250Mb/s-to-3.4Gb/s HDMI receiver with adaptive loop updating frequencies and an adaptive equalizer

A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery

Session 11 Overview TD: Trends in wireless communications

A GHz spintronic-based RF oscillator

A remote-powered RFID tag with 10Mb/s UWB uplink and −18.5dBm sensitivity UHF downlink in 0.18µm CMOS

A pulsed UWB receiver SoC for insect motion control

Towards terahertz operation of CMOS

A 2.75mW wideband correlation-based transceiver for body-coupled communication

A 128b organic RFID transponder chip, including Manchester encoding and ALOHA anti-collision protocol, operating with a data rate of 1529b/s

Organic CMOS circuits for RFID applications

Silicon-resonator-based, 3µA real-time clock with ±5ppm frequency accuracy

A 500µW neural tag with 2µV AFE and frequency-multiplying MICS/ISM FSK transmitter

Session 12 Overview RF building blocks

A low-noise active balun with IM2 cancellation for multiband portable DVB-H receivers

A 3.6mW differential common-gate CMOS LNA with positive-negative feedback

A compact low-noise weighted distributed amplifier in CMOS

A 0.2-to-2.0GHz 65nm CMOS receiver without LNA achieving ≫11dBm IIP3 and ≪6.5 dB NF

A 0.6V 380µW −14dBm LO-input 2.4GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combiner

A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOS

A 0.75V 325µW 40dB-SFDR frequency-hopping synthesizer for wireless sensor networks in 90nm CMOS

A software-defined radio receiver architecture robust to out-of-band interference

A 400-to-900 MHz receiver with dual-domain harmonic rejection exploiting adaptive interference cancellation

Session 13 Overview Flash memory

A $172mm^{2}$ 32Gb MLC NAND flash memory in 34nm CMOS

A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD

A 48nm 32Gb 8-level NAND flash memory with 5.5MB/s program throughput

A 113mm2 32Gb 3b/cell NAND flash memory

A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking

A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS

Session 14 Overview Digital wireless and reconfigurability

A reconfigurable, 0.13µm CMOS 110pJ/pulse, fully integrated IR-UWB receiver for communication and sub-cm ranging

A 0.55V 16Mb/s 1.6mW non-coherent IR-UWB digital baseband with ±1ns synchronization accuracy

A 110nm RFCMOS GPS SoC with 34mW −165dBm tracking sensitivity

A 0.13µm CMOS 655Mb/s 4×4 64-QAM K-Best MIMO detector

A 1GHz digital channel multiplexer for satellite OutDoor Unit based on a 65nm CMOS transceiver

A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS

Session 15 Overview Display and imager electronics

A piecewise-linear 10b DAC architecture with drain-current modulation for compact AMLCD driver ICs

A 10b column driver with variable-current-control interpolation for mobile active-matrix LCDs

A 0.1e- vertical FPN 4.7e- read noise 71dB DR CMOS image sensor with 13b column-parallel single-ended cyclic ADCs

A digital driving technique for an 8b QVGA AMOLED display using ΔΣ modulation

Session 16 Overview High-speed mm-wave circuits

An 18Gb/s duobinary receiver with a CDR-assisted DFE

A 43.7mW 96GHz PLL in 65nm CMOS

An array of 4 complementary LC-VCOs with 51.4% W-Band coverage in 32nm SOI CMOS

A mm-wave CMOS multimode frequency divider

A 128.24-to-137.00GHz injection-locked frequency divider in 65nm CMOS

Session 17 Overview TD: Energy-aware sensor systems

A robust wireless sensor node for in-tire-pressure monitoring

A release-on-demand wireless CMOS drug delivery SoC based on electrothermal activation technique

A 5.2mW self-configured wearable body sensor network controller and a 12µW 54.9% efficiency wirelessly powered sensor for continuous health monitoring system

An integrated power supply system for low-power 3.3V electronics using on-chip polymer electrolyte membrane (PEM) fuel cells

A mm-sized implantable power receiver with adaptive link compensation

An efficient piezoelectric energy-harvesting interface circuit using a bias-flip rectifier and shared inductor

An energy-aware multiple-input power supply with charge recovery for energy harvesting applications

Integrated capacitive power-management circuit for thermal harvesters with output power 10 to 1000µW

An optically programmable SoC for an autonomous $mm^{3}-sized$ microrobot

Session 18 Overview Ranging and Gb/s communication

A fully integrated 24GHz UWB radar sensor for automotive applications

A single-chip dual-band 22-to-29GHz/77-to-81GHz BiCMOS transceiver for automotive radars

A 77GHz transceiver in 90nm CMOS

A 1.1nJ/b 802.15.4a-compliant fully integrated UWB transceiver in 0.13µm CMOS

A 90nm CMOS low-power 60GHz transceiver with integrated baseband circuitry

A low-power fully integrated 60GHz transceiver system with OOK modulation and on-board antenna assembly

A 2.88Gb/s digital hopping UWB transceiver

Session 19 Overview Analog techniques

A chopper current-feedback instrumentation amplifier with a 1mHz 1/ƒ noise corner and an AC-coupled ripple-reduction loop

A 140dB-CMRR current-feedback instrumentation amplifier employing ping-pong auto-zeroing and chopping

A 150pW program-and-hold timer for ultra-low-power sensor platforms

A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47µW at 0.6V

A 25mA 0.13µm CMOS LDO regulator with power-supply rejection better than −56dB up to 10MHz using a feedforward ripple-cancellation technique

A sub-1V bandgap voltage reference in 32nm FinFET technology

A 90nm CMOS CT BPF for Bluetooth transceivers with DT 1b-switched-resistor cutoff-frequency control

A 1.25mW 75dB-SFDR CT filter with in-band noise reduction

Session 20 Overview Sensors and MEMS

A 1.05V 1.6mW 0.45°C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOS

A CMOS smart temperature sensor with a batch-calibrated inaccuracy of ±0.25°C (3σ) from −70°C to 130°C

An interface for a 300°/s capacitive 2-axis micro-gyroscope with pseudo-CT readout

An instrument-on-chip for impedance measurements on nanobiosensors with attoFarad resoution

20.5 A Sub-pA ΔΣ Current Amplifier for Single-Molecule Nanosensors

A compact CMOS MEMS microphone with 66dB SNR

A 2×32 range-finding sensor array with pixel-inherent suppression of ambient light up to 120klx

A 0.25µm logarithmic CMOS imager for emissivity-compensated thermography

Session 21 overview 10-to-40Gb/s transmitters and recievers

A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems

A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS

A 40Gb/s full-rate 2:1 MUX in 0.18µm CMOS

An 80mW 40Gb/s 7-Tap T/2-Spaced FFE in 65nm CMOS

A 20Gb/s full-rate linear CDR circuit with automatic frequency acquisition

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS

21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber

Session 22 overview PA and antenna interface

A 0.13µm CMOS power amplifier with ultra-wide instantaneous bandwidth for imaging applications

An octave-range watt-level fully integrated CMOS switching power mixer array for linearization and back-off efficiency improvement

A single-chip highly linear 2.4GHz 30dBm power amplifier in 90nm CMOS

A 60GHz-band 1V 11.5dBm power amplifier with 11% PAE in 65nm CMOS

50-to-67GHz ESD-protected power amplifiers in digital 45nm LP CMOS

A CMOS adaptive antenna-impedance-tuning IC operating in the 850MHz-to-2GHz band

A tunable integrated duplexer with 50dB isolation in 40nm CMOS

Session 23 Overview PLLs and clocks

A 1MHz-bandwidth type-I ΔΣ fractional-N synthesizer for WiMAX applications

A 2.2GHz 7.6mW sub-sampling PLL with −126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18µm CMOS

An edge-missing compensator for fast-settling wide-locking-range PLLs

A 975-to-1960MHz fast-locking fractional-N synthesizer with adaptive bandwidth control and 4/4.5 prescaler for digital TV tuners

A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation

A leakage-suppression technique for phase-locked systems in 65nm CMOS

A precision relaxation oscillator with a self-clocked offset-cancellation scheme for implantable biomedical SoCs

An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage

Session 24 Overview Wireless connectivity

A $2mm^{2}$ 0.1-to-5GHz SDR receiver in 45nm digital CMOS

A 65nm CMOS inductorless triple-band-group WiMedia UWB PHY

A reconfigurable demodulator with 3-to-5GHz agile synthesizer for 9-band WiMedia UWB in 65nm CMOS

A highly integrated low-power 2.4GHz transceiver using a direct-conversion diversity receiver in 0.18µm CMOS for IEEE802.15.4 WPAN

A fully integrated 2×2 MIMO dual-band dual- mode direct-conversion CMOS transceiver for WiMAX/WLAN applications

A 1.1V 5-to-6GHz reduced-component direct-conversion transmit signal path in 45nm CMOS

A 2.4GHz 2Mb/s versatile PLL-based transmitter using digital pre-emphasis and auto calibration in 0.18µm CMOS for WPAN

A 7.2mW quadrature GPS receiver in 0.13µm CMOS

A 10.8mW body-channel-communication/MICS dual-band transceiver for a unified body-sensor-network controller

Session 25 Overview Medical

A wireless and batteryless 130mg 300µW 10b implantable blood-pressure-sensing microsystem for real-time genetically engineered mice monitoring

A wireless IC for time-share chemical and electrical neural recording

A flexible clockless 32-ch simultaneous wireless neural recording system with adjustable resolution

A biomedical multiprocessor SoC for closed-loop neuroprosthetic applications

A CMOS fluorescent-based biosensor microarray

A frequency-shift CMOS magnetic biosensor array with single-bead sensitivity and no external magnet

Session 26 Overview Switched-mode techniques

Multiple-output step-up/down switching DC-DC converter with vestigial current control

Single-inductor dual-input dual-output buck-boost fuel-cell-li-ion charging DC-DC converter supply

Digitally assisted quasi-V2 hysteretic buck converter with fixed frequency and without using large-ESR capacitor

A 20W/channel Class-D amplifier with significantly reduced common-mode radiated emissions

Two Class-D audio amplifiers with 89/90% efficiency and 0.02/0.03% THD+N consuming less than 1mW of quiescent power

A 460W Class-D output stage with adaptive gate drive

Session 27 Overview SRAM and emerging memory

A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management

A process-variation-tolerant dual-power-supply SRAM with $0.179µm^{2}$ Cell in 40nm CMOS using level-programmable wordline driver

A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology

A 90nm 12ns 32Mb 2T1MTJ MRAM

A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes

Session 28 Overview TD: Directions in computing and signaling

Optical I/O technology for tera-scale computing

Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing

A stretchable EMI measurement sheet with 8×8 coil array, 2V organic CMOS decoder, and −70dBm EMI detection circuits in 0.18¼m CMOS

Field-coupled nanomagnets for interconnect-free nonvolatile computing

Chip Scale Camera Module (CSCM) using Through-Silicon-Via (TSV)

A subjective-contour generation LSI system with expandable pixel-parallel architecture for vision systems

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM

Session 29 Overview mm-wave circuits

A 1.1V 150GHz amplifier with 8dB gain and +6dBm saturated output power in standard digital 65nm CMOS using dummy-prefilled microstrip lines

W-band CMOS amplifiers achieving +10dBm saturated output oower and 7.5dB NF

A 26dB-gain 100GHz Si/SiGe Cascaded Constructive-Wave Amplifier

A dual-mode architecture for a phased-array receiver based on injection locking in 0.13µm CMOS

A digitally controlled compact 57-to-66GHz front-end in 45nm digital CMOS

A 57-to-66GHz quadrature PLL in 45nm digital CMOS

A 59GHz push-push VCO with 13.9GHz tuning range using loop-ground transmission line for a full-band 60GHz transceiver

Low-voltage analog and mixed-signal CMOS circuit design

F1: SSD memory subsystem innovation

F2: Medical image sensors

F3: GIRAFE: 4G RF frontends

F4: Ultra-low-voltage-circuit design

F5: ATAC: High-speed interfaces

F6: Multi-domain processors

F7: Clock synthesis design

F8: Integrated neural interfaces

SE1: Healthy Radios: Radio & microwave devices for the health sciences

SE2: Is fabless MEMS fabulous?

SE3: Will ADCs overtake binary frontends in backplane signaling?

SE4: Highlights of IEDM 2008

E1: Forewarned is four armed: Classic Analog misteakes to avoid

SE5 things all RFIC designers should know (But are afraid to ask)

SE6: Interleaving ADC's - exploiting the parallelism

SE7: Next generation energy scavenging systems

E2: MID - ‘Scaled down’ PC or ‘Souped up'’ handheld?

Index to authors

Executive committee

Program committee

Call for papers

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A 0.1e- vertical FPN 4.7e- read noise 71dB DR CMOS image sensor with 13b column-parallel single-ended cyclic ADCs

Content Provider	IEEE Xplore Digital Library
Author	Jong-Ho Park Aoyama, S. Watanabe, T. Akahori, T. Kosugi, T. Isobe, K. Kaneko, Y. Zheng Liu Muramatsu, K. Matsuyama, T. Kawahito, S.
Copyright Year	2009
Description	Author affiliation: Brookman Lab, Hamamatsu, Japan (Jong-Ho Park; Aoyama, S.; Watanabe, T.; Akahori, T.; Kosugi, T.; Isobe, K.; Kaneko, Y.; Zheng Liu; Muramatsu, K.; Matsuyama, T.; Kawahito, S.)
Abstract	The performance requirements of next-generation CMOS image sensors (CIS) have been increasing in terms of frame rate, read noise, dynamic range, as well as pixel resolution. In order to satisfy strict specifications, a column-parallel ADC is a key element in a state-of-the-art CIS. However, this architecture leads to side-effects such as vertical fixed pattern noise (VFPN) and read noise. In order to reduce these non-idealities, several techniques can be applied such as digital CDS using a single-slope ADC [1][2], and pre-amplified digital CDS using a SAR ADC [3]. It is challenging to overcome the difficulty of compatibility between ADC speed and bit resolution, while maintaining low-noise performance and high dynamic range (DR). In this paper, a low-noise high-DR and high-speed CIS with a 13b column-parallel cyclic ADC based on a single-ended architecture is presented. The cyclic ADC requires 12 cycles for 13b resolution. The ADC requires identical conversions for reset and signals, within the limited horizontal time period, at a frame rate of over 300fps, so as to achieve perfect digital CDS and ultra-low VFPN. In addition, lower total read noise is achieved without signal amplification by removing: 1) dual analog paths in fully differential circuits, 2) a common reference route, and 3) digital coupling noise. Published cyclic ADCs that are located in the column of a CIS have column pitch of 15µm or larger [4]. The circuits with the single-ended architecture presented in this paper are squeezed into 5.6µm column pitch and can be applied to 2.8µm-pitch pixels with double-side disposition.
File Size	850541
File Format	PDF
ISBN	9781424434589
DOI	10.1109/ISSCC.2009.4977411
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-02-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS image sensors Capacitors Image converters Circuits Switches Dynamic range Computational Intelligence Society Linearity Signal resolution Image sampling
Content Type	Text
Resource Type	Article

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