NDLI: 200 Mb wafer memory

Content Provider	IEEE Xplore Digital Library
Author	MacDonald, N. Neish, G. Sinclair, A. Baba, F. Tatematsu, T. Hirawa, K. Miyasaka, K.
Copyright Year	1989
Description	Author affiliation: Anamartic Ltd., Cambridge, UK (MacDonald, N.; Neish, G.; Sinclair, A.)
Abstract	The realization of a high-capacity whole-wafer memory is described, including wafer configuration, chip architecture, process technology, and performance. The wafer is essentially a single-ported serial memory device. An innovative concept which utilizes any defective chips free from power failures has made possible a high-yield wafer-scale memory. The wafer includes an array of chips which have a DRAM (dynamic RAM) core and additional control logic known as the configuration logic (Conlog). Each Conlog is connected to its four neighbors by signal lines, which form logic networks on the wafer. An external controller transmits commands to each Conlog element to set up links between chips and configure a single contiguous data path known as a spiral. The spiral is configured on completion of wafer processing by external control software which implements chip test and linking of chips as a single-shaped data-flow chain. The DRAM core and Conlog are designed using a standard 1-Mb DRAM fabricated by the 1.3- mu m CMOS process. The waveform of the internal clock and output of the DRAM are shown as well as the output waveform of the receive terminal of Conlog.
Starting Page	240
Ending Page	241
File Size	368787
Page Count	2
File Format	PDF
DOI	10.1109/ISSCC.1989.48272
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-02-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Logic arrays Logic devices Spirals DRAM chips Process control Software testing Joining processes CMOS process Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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