NDLI: A 20 MIPS sustained 32 b CMOS microprocessor with 64 b data bus

Content Provider	IEEE Xplore Digital Library
Author	Jouppi, N.P. Tang, J.Y.F. Dion, J.
Copyright Year	1989
Description	Author affiliation: Digital Equipment Corp., Palo Alto, CA, USA (Jouppi, N.P.; Tang, J.Y.F.; Dion, J.)
Abstract	The authors describe a full-custom 32-b microprocessor which uses a 1.5- mu m drawn n-well CMOS technology with single polycide and two levels of metal. The die size is 7.76 mm*6.21 mm and contains 180 k transistors, of which 150 k are used in the cache or register file. The CPU executes an RISC instruction set with simple and regular encoding. The chip has been designed for operation at 20 MIPS (million instructions per second), running large benchmarks in a complete system. Power dissipation at 25 degrees C with a 5-V supply is under 3 W. The chip has 136 signal, 16 power, and 16 ground pads and is packaged in a 176-pin plastic pin-grid-array package with eight decoupling capacitors. The CPU pipeline and machine organization and the instruction fetch pipestage are shown.
Starting Page	84
Ending Page	85
File Size	893027
Page Count	2
File Format	PDF
DOI	10.1109/ISSCC.1989.48192
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-02-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microprocessors CMOS technology Plastic packaging Packaging machines Registers Reduced instruction set computing Encoding Power dissipation Capacitors Pipelines
Content Type	Text
Resource Type	Article

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