NDLI: Performance issues of SOI CMOS circuits at low supply voltages

Content Provider	IEEE Xplore Digital Library
Author	Abel, H.B. Zimmer, G.
Copyright Year	1993
Description	Author affiliation: Dept. of Electron Devices and Circuits, Duisburg Univ., Germany (Abel, H.B.; Zimmer, G.)
Abstract	Circuit applications working at typical battery voltages (1.35...1.55 V) promise to be an interesting market for SOI technology. Reduced extrinsic capacitances, low leakage currents, nearly ideal subthreshold slopes and improved scalability offer several advantages over conventional CMOS circuits, particularly in regard of power consumption and circuit speed In this paper we use the SPICE implementation of our charge sheet model of the thin-film SOI MOSFET to investigate quantitatively the performance of digital SOI CMOS circuits in the voltage range from 1 to 2 V. The charge sheet principle allows us to include the subthreshold range into the simulation without losing the consistency with well established strong inversion models. The calculations are based on a SIMOX process with t/sub of/=20 nm, t/sub b/=80 nm, t/sub ob/=350 nm. The threshold voltages of the n-channel and p-channel transistors are assumed to be 0.4 V and 0.5 V, respectively. Most of the model parameters for both SOI and bulk silicon MOS devices-the latter ones are described with the SPICE Level 3 MOSFET model-have been extracted from numerical device simulations.
Starting Page	104
Ending Page	105
File Size	132937
Page Count	2
File Format	PDF
ISBN	0780313461
DOI	10.1109/SOI.1993.344572
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-10-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Low voltage CMOS digital integrated circuits SPICE Semiconductor device modeling MOSFET circuits Batteries CMOS technology Capacitance Leakage current Scalability
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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