NDLI: Hot-carrier currents of SOI MOSFETs

Content Provider	IEEE Xplore Digital Library
Author	Hsing-Jen Wann King, J. Jian Chen Ko, P.K. Chenming Hu
Copyright Year	1993
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA (Hsing-Jen Wann; King, J.; Jian Chen; Ko, P.K.; Chenming Hu)
Abstract	MOSFETs built on the SOI structure exhibit superior short channel behaviors over the bulk MOSFETs. They also have other advantages such as reduction of the junction capacitance, radiation hardness and ease for device isolation. The SOI MOSFET is a promising candidate for future device scaling. The hot-carrier effect that increases with device miniaturization is another important device scaling constraint that has to be considered for the SOI MOSFET. The hot-carrier effect, which is usually monitored by the substrate current for the NMOSFET and the gate current for the PMOSFET for bulk devices, are closely related to the high channel electric field near the drain. The quasi-two-dimensional (quasi-2D) model provides the link between the hot-carrier currents and the device design parameters for the bulk MOSFETs. This model is refined by considering the 2D effect and the lateral doping gradient effect separately.
Starting Page	118
Ending Page	119
File Size	167778
Page Count	2
File Format	PDF
ISBN	0780313461
DOI	10.1109/SOI.1993.344568
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-10-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hot carriers MOSFET circuits Hot carrier effects Substrates Silicon Semiconductor films Predictive models Semiconductor process modeling Doping Contracts
Content Type	Text
Resource Type	Article

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A channel field model of SOI MOSFET

Special mechanisms in thin film SOI MOSFETs

The role of externally applied body-bias on the hot-carrier degradation of partially depleted SOI N-MOSFETs

Comparison of hot-carrier degradation effects in inversion-mode and accumulation-mode fully depleted SOI MOSFETs

A Single-Halo Dual-Material Gate SOI MOSFET

Two-dimensional analytical modeling of nanoscale electrically-shallow junction (EJ) fully depleted SOI MOSFET

Analytical model for the threshold voltage of dual material gate (DMG) partially depleted SOI MOSFET and evidence for reduced short-channel effects

Hot-carrier effects in 0.15/spl mu/m low dose SIMOX N-MOSFETs

Substrate floating effects of p-channel SOI MOSFETs

Hot-carrier currents of SOI MOSFETs

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Special mechanisms in thin film SOI MOSFETs

The role of externally applied body-bias on the hot-carrier degradation of partially depleted SOI N-MOSFETs

Comparison of hot-carrier degradation effects in inversion-mode and accumulation-mode fully depleted SOI MOSFETs

A Single-Halo Dual-Material Gate SOI MOSFET

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