NDLI: Study of fin-tunnel FETs with doped pocket as capacitor-less 1T DRAM

Content Provider	IEEE Xplore Digital Library
Author	Biswas, Arnab Ionescu, Adrian M.
Copyright Year	2014
Description	Author affiliation: STI-IEL-NANOLAB, Ecole Polytechnique Fédérale de Lausanne, Switzerland (Biswas, Arnab; Ionescu, Adrian M.)
Abstract	In this work we propose and validate by experimentally calibrated simulations a silicon Tunnel FET(TFET) based capacitorless DRAM cell, implemented as a fully-depleted FinFET with CMOS compatible process. The devices have a conventional FinFET structure except for a p+ (for n-type TFET) doped pocket of length L and doping NPKT between the intrinsic channel and the (n++) drain. This doped pocket creates a necessary condition to store holes injected from the source-to-body junction. In [1], there was a need to induce a potential well in order to store the excess charges; whereas in the present case a potential well is permanently present due to the doped pocket. The drain voltage is used as a control voltage to either fill the potential well with carriers (WRITE “1”) by attracting holes from the p++ source or repel them to empty the well of carriers (WRITE “0”). In contrast with the SOI Z-RAM® there is no need of impact ionization to create/inject the hole charge in the device body, the holes being injected by the forward-bias p+i junction, which significantly improves the device reliability. Measurements on FDSOI TFET devices as reported in [1,2] were performed at elevated temperatures and used to calibrate the non-local band-to-band (B2B) tunnelling model in Sentaurus TCAD [3]. The retention characteristics of the proposed memory cell is simulated at an elevated temperature of 85°C and is shown to be not degrading at higher temperature as is the case in conventional capacitorless DRAMs [4].
Starting Page	1
Ending Page	2
File Size	926156
Page Count	2
File Format	PDF
ISBN	9781479974399
DOI	10.1109/S3S.2014.7028203
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field effect transistors Random access memory Temperature Doping Temperature measurement Temperature dependence Resistance
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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