NDLI: 3D memory with shared lithography steps: The memory industry's plan to “cram more components onto integrated circuits”

Content Provider	IEEE Xplore Digital Library
Author	Sekar, Deepak C.
Copyright Year	2014
Description	Author affiliation: Rambus Labs, USA (Sekar, Deepak C.)
Abstract	In his 1965 paper titled “cramming more components onto integrated circuits” [1], Gordon Moore predicted the number of components on a chip would increase exponentially with time due to continual reduction of feature sizes. That paradigm has continued successfully for the past 50 years, but cracks are starting to appear. Lithography is becoming prohibitively expensive and component quality is expected to degrade significantly beyond the 7nm node. To lower cost per bit further without relying on feature size scaling, monolithic 3D flash memories are being introduced where lithography steps are shared among multiple memory layers. In this paper, I review the flash memory industry's direction and describe 3D concepts that can scale other parts of the memory hierarchy.
Starting Page	1
Ending Page	3
File Size	1153890
Page Count	3
File Format	PDF
ISBN	9781479974399
DOI	10.1109/S3S.2014.7028196
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Three-dimensional displays Random access memory Lithography Flash memories Memory management Microprocessors
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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3D memory with shared lithography steps: The memory industry's plan to “cram more components onto integrated circuits”