NDLI: Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Hiienkari, Markus Teittinen, Jukka Koskinen, Lauri Turnquist, Matthew Kaltiokallio, Mikko Makipaa, Jani Rantala, Arto Sopanen, Matti
Copyright Year	2014
Description	Author affiliation: University of Turku, Technology Research Center, Joukahaisenkatu 1C, 20520, Finland (Hiienkari, Markus; Teittinen, Jukka; Koskinen, Lauri) \|\| Aalto University, Department of Micro and Nanosciences, Finland (Turnquist, Matthew; Kaltiokallio, Mikko) \|\| VTT Technical Research Centre of Finland, Finland (Makipaa, Jani; Rantala, Arto; Sopanen, Matti)
Abstract	To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.
Starting Page	1
Ending Page	2
File Size	1139013
Page Count	2
File Format	PDF
ISBN	9781479974399
DOI	10.1109/S3S.2014.7028192
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Timing Central Processing Unit Energy measurement Latches Voltage measurement Energy consumption
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

Fully integrated DC-DC converter and a 0.4V 32-bit CPU with timing-error prevention supplied from a prototype 1.55V Li-ion battery

A CMOS 8-bit 20MHz two-step parallel A/D converter with 95mW power consumption

A 5-bit 1.35-GSPS DAC for UWB transceivers

A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention

An energy-efficient resilient flip-flop circuit with built-in timing-error detection and correction

A 0.75-V, 0.7 MHz CMOS 32-bit RISC microprocessor for portable applications

Ultra-low voltage datapath blocks in 28nm UTBB FD-SOI

A low-voltage 32/spl times/32-bit multiplier in dynamic differential logic

Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS

Similar Documents

A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

Fully integrated DC-DC converter and a 0.4V 32-bit CPU with timing-error prevention supplied from a prototype 1.55V Li-ion battery

A CMOS 8-bit 20MHz two-step parallel A/D converter with 95mW power consumption

A 5-bit 1.35-GSPS DAC for UWB transceivers

A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention

An energy-efficient resilient flip-flop circuit with built-in timing-error detection and correction

A 0.75-V, 0.7 MHz CMOS 32-bit RISC microprocessor for portable applications

Ultra-low voltage datapath blocks in 28nm UTBB FD-SOI

A low-voltage 32/spl times/32-bit multiplier in dynamic differential logic

Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS