NDLI: 45 GHz silicon MESFETs on a 0.15 µm SOI CMOS process

Content Provider	IEEE Xplore Digital Library
Author	Lepkowski, W. Wilk, S.J. Thornton, T.J.
Copyright Year	2009
Description	Author affiliation: Arizona State University, PO Box 876206, Tempe, AZ 85281, USA (Lepkowski, W.; Wilk, S.J.)
Abstract	Fully integrated MESFETs have been shown to work on multiple commercial silicon-on-insulator (SOI) and silicon-on-sapphire (SOS) CMOS processes without changing a step in the process flow [1–3]. The unique features of the MESFET including depletion mode operation, breakdown voltages in excess of 50 V, and easy to adjust, but well controlled threshold voltages have given the designers a cost-free way to achieve certain circuit design solutions that were previously cost inefficient or difficult to implement on their respective processes [2,4]. Until now, silicon MESFET based circuit applications were limited in very high frequency applications due to either the technology they were designed on and/or key layout rules that affected the gate length, L, of the MESFETs but not the MOSFETs. The highest SOI MESFET f reported was ∼10 GHz which was associated with an L = 0.4 µm on a 0.35 µm SOI CMOS process [1,2]. The devices presented in this abstract were designed on a 0.15 µm process and represent the most aggressive scaling yet for SOI MESFETS. Devices with f ≫ 45 GHz and L = 0.15 µm were achieved.
Starting Page	1
Ending Page	2
File Size	444963
Page Count	2
File Format	PDF
ISBN	9781424442560
ISSN	1078621X
DOI	10.1109/SOI.2009.5318754
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS process Silicon on insulator technology Voltage control Threshold voltage Circuit synthesis Costs MESFET integrated circuits MESFET circuits VHF circuits Frequency
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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