NDLI: Platinum silicide metallic source & drain process optimization for FDSOI pMOSFETs

Content Provider	IEEE Xplore Digital Library
Author	Carron, V. Nemouchi, F. Morand, Y. Poiroux, T. Vinet, M. Bernasconi, S. Louveau, O. Lafond, D. Delaye, V. Allain, F. Minoret, S. Vandroux, L. Billon, T.
Copyright Year	2009
Description	Author affiliation: STMicroelectronics - 850, rue Jean Monnet - 38926 Crolles - France (Morand, Y.; Bernasconi, S.; Louveau, O.) \|\| CEA-LETI/Minatec - 17 rue des Martyrs - 38054 Grenoble Cedex 9 - France (Carron, V.; Nemouchi, F.; Poiroux, T.; Vinet, M.; Lafond, D.; Delaye, V.; Allain, F.; Minoret, S.; Vandroux, L.; Billon, T.)
Abstract	We report on the development of a metallic source and drain module for FDSOI pMOSFETs including lateral PtSi formation, Ti/TiN barrier, optimized doping conditions, controlled PtSi penetration below spacers and suitable cleaning of the PtSi surface prior to barrier deposition. Mean specific contact resistivity values lower than $2Ωµm^{2}$ have been achieved, which leads to highly performant pMOSFET devices $(I=345µA.µm^{-}$ $^{1}/Ioff=30nA.µm^{−1}$ at -1V for 50nm gate length).
Starting Page	1
Ending Page	2
File Size	2427145
Page Count	2
File Format	PDF
ISBN	9781424442560
ISSN	1078621X
DOI	10.1109/SOI.2009.5318748
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Platinum Silicides MOSFETs Tin Cleaning Electrical resistance measurement Contact resistance Doping Silicon Implants
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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