NDLI: Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping

Content Provider	IEEE Xplore Digital Library
Author	Chun-Ming Huang Kuen-Jong Lee Chih-Chyau Yang Wen-Hsiang Hu Shi-Shen Wang Jeng-Bin Chen Chi-Shi Chen Van, L.-D. Chien-Ming Wu Wei-Chang Tsai Jing-Yang Jou
Copyright Year	2006
Description	Author affiliation: Nat. Chip Implementation Center (CIC), Nat. Appl. Res. Labs., Hsinchu (Chun-Ming Huang)
Abstract	In this paper, we propose a novel SoC design methodology referred to as multi-project system-on-a-chip (MP-SoC), which can integrate multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced due to the sharing of a common SoC platform. The design flows for the system architecture, individual IP blocks, as well as the logic and physical implementations of MP-SoC are explored. The isolation mechanism to prevent interference among the IPs and the arbitration mechanism to grant the bus usage for master IPs are also presented. A test chip named MP-SoC-l that includes 8 SoC projects from 4 universities was selected as a demonstration example for verifying the MP-SoC design concept. This chip is designed and implemented in TSMC 0.13 mum CMOS generic logic process technology, and the total silicon area for MP-SoC-l test chip is 4950 mum x 4938 mum. Experimental results of MP-SoC-l test chip show that all projects are successfully implemented in the common platform and 82.91% silicon area is saved with this MP- SoC methodology as compared with the case where multiple SoC projects are fabricated individually.
Starting Page	137
Ending Page	140
File Size	470800
Page Count	4
File Format	PDF
ISBN	0780397819
DOI	10.1109/SOCC.2006.283867
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip System testing Vehicles Silicon Prototypes Logic design Logic testing Design methodology Costs Interference
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Programmable System-on-Chip for Silicon Prototyping

Programmable System-on-Chip (SoC) for silicon prototyping

PrSoC: Programmable System-on-chip (SoC) for silicon prototyping

A novel methodology for Multi-Project System-on-a-Chip

Silicon virtual prototyping: the new cockpit for nanometer chip design [SoC]

Implementation and prototyping of a complex multi-project system-on-a-chip

A configurable prototyping platform for multi-project system-on-a-chip

Project Spinnaker: a new generation of rapid prototyping system

A user-configurable framework for testing prototype system-on-chip implementations

Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping

Similar Documents

Programmable System-on-Chip for Silicon Prototyping

Programmable System-on-Chip (SoC) for silicon prototyping

PrSoC: Programmable System-on-chip (SoC) for silicon prototyping

A novel methodology for Multi-Project System-on-a-Chip

Silicon virtual prototyping: the new cockpit for nanometer chip design [SoC]

Implementation and prototyping of a complex multi-project system-on-a-chip

A configurable prototyping platform for multi-project system-on-a-chip

Project Spinnaker: a new generation of rapid prototyping system

A user-configurable framework for testing prototype system-on-chip implementations

Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping