NDLI: Experiences in simulating a declarative multiprocessor

Content Provider	IEEE Xplore Digital Library
Author	Tan, G.S.H. Teo, Y.M.
Copyright Year	1995
Description	Author affiliation: Dept. of Inf. Syst. & Comput. Sci., Nat. Univ. of Singapore, Singapore (Tan, G.S.H.; Teo, Y.M.)
Abstract	There has been extensive research into nonconventional, non-von Neumann parallel computer architectures and declarative programming languages. Dataflow and reduction multiprocessors are examples of such machines which exhibit novel architectures. The Flagship parallel reduction machine is one such multiprocessor using a packet-based graph reduction model of computation to exploit the parallelism inherent in functional languages. A functional simulator for the Flagship machine has been written for studying the functional characteristics of the machine. However, the functional simulator only simulates the actions of the executional units, with no notion of the time involved. For performance evaluation, timing characteristics must be monitored. This paper describes a technique for introducing an event-driven timing scheme into the functional simulator. With the introduction of such a scheme, certain synchronisation issues arise due to the functionality of the simulator. This paper also describes ways of resolving these issues. The architecture is MIMD, based on a set of tightly-coupled processor-store pairs interconnected by a delta network. This is a commonly used architecture, so anyone intending to simulate a similar architecture can draw from the experiences as related in this paper.
Starting Page	95
Ending Page	104
File Size	879443
Page Count	10
File Format	PDF
ISBN	0818670916
DOI	10.1109/SIMSYM.1995.393590
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-04-09
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computational modeling Timing Computer architecture Concurrent computing Discrete event simulation Information systems Computer science Monitoring LAN interconnection Computer languages
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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