NDLI: Estimating rollback overhead for optimism control in Time Warp

Content Provider	IEEE Xplore Digital Library
Author	Ferscha, A. Luthi, J.
Copyright Year	1995
Description	Author affiliation: Inst. fur Angewandte Inf. und Informationssyst., Wien Univ., Austria (Ferscha, A.; Luthi, J.)
Abstract	The main performance pitfall of the Time Warp distributed discrete event simulation (DDES) protocol has been widely recognized to be the overoptimistic progression of event execution into the simulated future. The premature execution of events that eventually have to be "rolled back" due to causality violations induces memory and communication overheads as sources of performance inefficiencies. Optimistic Time Windows and self adaptive mechanisms have been proposed in the literature to control the optimism in Time Warp in order to improve or optimize its execution performance. An adaptive optimism control mechanism based on the observed model parallelism is proposed. Methodologically, logical processes (LPs) monitor the local virtual time (LVT) progression per unit CPU time from the timestamp of arriving messages and establish a cost model for the tradeoff between optimistically progressing and conservatively blocking the simulation engine. Compared to previous approaches, an optimal CPU delay interval is computed from the rollback probability and the overhead induced by the rollback procedure, such that the LP can adapt the synchronization behavior to the amount of optimism that can be justified from the parallelism inherent in the simulation model. Experiments with an implementation on a distributed memory multiprocessor (iPSC/860) show that the protocol is able to automatically adjust the local virtual time progression such that rollback overhead is minimized, and that the original Time Warp protocol can be outperformed.
Starting Page	2
Ending Page	12
File Size	1069455
Page Count	11
File Format	PDF
ISBN	0818670916
DOI	10.1109/SIMSYM.1995.393563
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-04-09
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Protocols Discrete event simulation Programmable control Adaptive control Communication system control Parallel processing Computational modeling Time warp simulation Cost function Optimization methods
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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