NDLI: Special purpose array processor for digital logic simulation

Content Provider	IEEE Xplore Digital Library
Author	Youngmin Hur Szygenda, S.A.
Copyright Year	1995
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA (Youngmin Hur; Szygenda, S.A.)
Abstract	Digital logic and fault simulation of large VLSI circuits is one of the most compute-intensive tasks in digital analysis. This paper describes a special purpose time driven array processor for digital logic simulation. The new architecture uses a massively parallel processing element (PE) array in a SIMD architecture. Compiled event-driven technology and nominal transport delay timing analysis are used. A circuit to be simulated is levelized according to the delay time order at the preprocessing stage and the levelized circuit is mapped into a massively parallel PE array. Circuit comparisons show that the speedup of the new architecture is up to 8 times faster than the MARS accelerator and it can be higher for increased circuit size; while the hardware cost remains low.
Starting Page	297
Ending Page	302
File Size	598220
Page Count	6
File Format	PDF
ISBN	0818670916
DOI	10.1109/SIMSYM.1995.393569
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-04-09
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic arrays Computational modeling Circuit simulation Computer architecture Delay Logic circuits Circuit faults Analytical models Very large scale integration Circuit analysis computing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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