NDLI: Partial expansion of dataflow graphs for resource-aware scheduling of multicore signal processing systems

Content Provider	IEEE Xplore Digital Library
Author	Zaki, G. Plishker, W. Bhattacharyya, S.S. Fruth, F.
Copyright Year	2014
Description	Author affiliation: ECE Dept., Univ. of Maryland, College Park, MD, USA (Zaki, G.; Plishker, W.; Bhattacharyya, S.S.) \|\| Multicore & Commun. Infrastruct. Bus. Unit, Texas Instrum. Inc., MD, USA (Fruth, F.)
Abstract	The complex design spaces associated with state-of-the-art, multicore signal processing systems pose significant challenges in realizing designs with high productivity and quality. The Partial Expansion Graph (PEG) implementation model was developed to help address these challenges by enabling more efficient exploration of the scheduling design space for multicore digital signal processors. The PEG allows designers and design tools to systematically adjust and adapt the amount of parallelism exposed from applications depending on the targeted platform. In this paper, we develop new algorithms for scheduling and mapping systems implemented using PEGs. Collectively, these algorithms operate in three steps. First, the amount of data parallelism in the application graph is tuned systematically over many iterations to profit from the available cores in the target platform. Then a mapping algorithm that uses graph analysis is developed to distribute data and task parallel instances over different cores while trying to balance the load of all processing units to make use of pipeline parallelism. Finally, we use a novel technique for performance evaluation by implementing the scheduler and a customizable solution on the programmable platform. We demonstrate the utility of our PEG-based scheduling and mapping algorithms through experiments on real application models and various synthetic graphs.
Starting Page	385
Ending Page	392
File Size	564639
Page Count	8
File Format	PDF
e-ISBN	9781479982974
DOI	10.1109/ACSSC.2014.7094469
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multicore processing Runtime Program processors Pipelines Schedules Processor scheduling Dynamic Scheduling Dataflow Graphs Digital Signal Processing Multiprocessor Scheduling
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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