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Design of m-out-of-n bit-voters

Content Provider	IEEE Xplore Digital Library
Author	Parhami, B.
Copyright Year	1991
Description	Author affiliation: Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA (Parhami, B.)
Abstract	Several synthesis methods for m-out-of-n bit-voting networks are described, and the costs of the resultant designs are compared. In the special case of majority voting (with gate count used as the cost index), it is shown that a multiplexer-based design method yields the best realizations for small n, while designs based on selection networks are most efficient when n is large. Other design techniques are offered that might be more efficient with particular technologies or when certain standard building blocks are to be used in the hardware realization. Most of these designs can be extended to the general case of unequal vote weights (weighted voting).
Starting Page	1260
Ending Page	1264
File Size	304270
Page Count	5
File Format	PDF
ISBN	0818624701
ISSN	10586393
DOI	10.1109/ACSSC.1991.186650
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-11-04
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voting Hardware Costs Circuits Computer networks Design engineering Network synthesis Design methodology Fault tolerant systems Algorithm design and analysis
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computer Networks and Communications

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