NDLI: Scheme for detecting CMOS stuck-open faults using single test patterns

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Scheme for detecting CMOS stuck-open faults using single test patterns

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Scheme for detecting CMOS stuck-open faults using single test patterns

Content Provider	IEEE Xplore Digital Library
Author	Cheema, M.S. Lala, P.K.
Copyright Year	1991
Description	Author affiliation: Dept. of Electr. Eng., NC A&T State Univ., Greensboro, NC, USA (Cheema, M.S.; Lala, P.K.)
Abstract	A technique for detection of stuck-open faults in CMOS circuits is presented. This approach needs only a single test pattern for detecting such faults, and the circuit retains its combinational characteristic. The problem of test invalidation by circuit delays, timing skews, etc., has been eliminated. Only two transistors and an additional input are needed to make any gate fully testable for all single stuck-open faults. Hence the area overhead is not significant. With a slight modification and a slightly greater increase in overhead the technique can be extended to detection of s-closed faults as well.
Starting Page	1251
Ending Page	1254
File Size	211555
Page Count	4
File Format	PDF
ISBN	0818624701
ISSN	10586393
DOI	10.1109/ACSSC.1991.186648
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-11-04
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault detection Circuit testing Circuit faults Electrical fault detection Logic testing CMOS technology Inverters CMOS logic circuits Delay Semiconductor device modeling
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computer Networks and Communications

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