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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Lee, B. Burgess, N. |
| Copyright Year | 2003 |
| Description | Author affiliation: Univ. of Wales, Cardiff, UK (Lee, B.; Burgess, N.) |
| Abstract | This paper presents results from the design of a parameterised function approximation unit on FPGA. The Taylor-series expansion is used to approximate a function f(x) of 8 to 26-bits over a given domain [a, b]. A search of the 1/sup st/, 2/sup nd/ and 3/sup rd/ order Taylor expansions is performed for each operand length to find the most area efficient implementation in terms of LUT usage of a representative FPGA technology. Results show that trading lookup-logic and arithmetic-logic reduces the exponential logic requirement that occurs if a predominantly ROM based approximation is used. |
| Starting Page | 2198 |
| Ending Page | 2202 |
| File Size | 301080 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780381041 |
| DOI | 10.1109/ACSSC.2003.1292370 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-11-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Function approximation Field programmable gate arrays Table lookup Taylor series Read only memory Convergence Optimization methods Equations Logic devices Signal generators |
| Content Type | Text |
| Resource Type | Article |
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