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Content Provider | IEEE Xplore Digital Library |
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Author | Tenca, A.F. Tawalbeh, L.A. |
Copyright Year | 2003 |
Description | Author affiliation: Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA (Tenca, A.F.; Tawalbeh, L.A.) |
Abstract | This paper presents the algorithm and architecture of a scalable radix-4 Montgomery multiplier. The straightforward implementation of a radix-4 design based on the techniques already published results in a poor solution. In this paper we present an algorithm and architecture for the scalable radix-4 multiplier that makes use of two types of digit receding in order to generate an efficient solution. The word-by-word algorithm used in the multiplier gives to the designer the freedom to select the level of parallelism according to the available area. Experimental results are shown to demonstrate that the proposed radix-4 Montgomery multiplier design has better area/performance tradeoff than previous radix-2 and 8 scalable designs. |
Starting Page | 1445 |
Ending Page | 1450 |
File Size | 533295 |
Page Count | 6 |
File Format | |
ISBN | 0780381041 |
DOI | 10.1109/ACSSC.2003.1292225 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2003-11-09 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Artificial intelligence Kernel Algorithm design and analysis Cryptography Arithmetic Design engineering Parallel processing Hardware Performance gain Buildings |
Content Type | Text |
Resource Type | Article |
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