NDLI: Massively parallel implementation of cyclic LDPC codes on a general purpose graphics processing unit

Content Provider	IEEE Xplore Digital Library
Author	Hyunwoo Ji Junho Cho Wonyong Sung
Copyright Year	2009
Description	Author affiliation: School of Electrical Engineering, Seoul National University, 599 Gwanak-ro, Gwanak-gu, 151-742, Korea (Hyunwoo Ji; Junho Cho; Wonyong Sung)
Abstract	Simulation of low-density parity-check (LDPC) codes frequently takes several days, thus the use of general purpose graphics processing units (GPGPUs) is very promising. However, GPGPUs are designed for compute-intensive applications, and they are not optimized for data caching or control management. In LDPC decoding, the parity check matrix H needs to be accessed at every node updating process, and the size of H matrix is often larger than that of GPU on-chip memory especially when the code-length is long or the weight is high. In this work, the parity check matrix of cyclic or quasi-cyclic LDPC codes is greatly compressed by exploiting the periodic property of the matrix. In our experiments, the Compute Unified Device Architecture (CUDA) of Nvidia is used. With the (1057, 813) and (4161, 3431) projective geometry (PG)—LDPC codes, the execution speed of the proposed method is more than twice of the reference implementations that do not exploit the cyclic property of the parity check matrices.
Starting Page	285
Ending Page	290
File Size	4303373
Page Count	6
File Format	PDF
ISBN	9781424443352
ISSN	15206130
DOI	10.1109/SIPS.2009.5336268
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-07
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parity check codes Graphics Decoding Computational modeling Computer architecture Concurrent computing Central Processing Unit Arithmetic Geometry Communication standards parallel processing Low-density parity-check (LDPC) codes Compute Unified Device Architecture (CUDA) general purpose graphics processing unit (GPGPU)
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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