NDLI: Fast pipeline schedule for an H.264 intra frame encoder with early termination

Content Provider	IEEE Xplore Digital Library
Author	Young-Joon Jo Jin-Su Jung Hyuk-Jae Lee
Copyright Year	2009
Description	Author affiliation: Inter-university Semiconductor Research Center, Department of Electrical Engineering, Seoul National University, Korea (Young-Joon Jo; Jin-Su Jung; Hyuk-Jae Lee)
Abstract	This paper presents a fast H.264 intra frame encoder that processes an HD720p size video at 30 fps with the operating clock frequency of 40 MHz. The low clock frequency is achieved by a novel intra prediction schedule that employs pipelining of the 4×4 predictions and the early termination of 16×16 prediction. The pipelining is achieved by the optimal processing order for 4×4 predictions that reduces bubbles between consecutive 4x4 predictions. Execution cycles of 16×16 prediction are reduced by early termination which uses the cost of 4×4 prediction as the stop condition. With the proposed schedule, the execution time of 16×16 prediction is saved by 49% for intra prediction of HD720p size videos. For further speed-up, the two least probable modes among nine 4×4 prediction modes are excluded. As a result, the required execution time is reduced to 370 cycles which are about 61 cycles faster than the previous best implementation.
Starting Page	109
Ending Page	114
File Size	4532394
Page Count	6
File Format	PDF
ISBN	9781424443352
ISSN	15206130
DOI	10.1109/SIPS.2009.5336234
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-07
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Termination of employment Costs Hardware Pipeline processing Clocks Frequency Interleaved codes Computer architecture Video coding Automatic voltage control block reordering H.264 intra prediction early termination pipeline schedule
Content Type	Text
Resource Type	Article

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