NDLI: Two-parallel concatenated BCH super-FEC architecture for 100-GB/S optical communications

Content Provider	IEEE Xplore Digital Library
Author	Sangho Yoon Hanho Lee Kihoon Lee Chang-Seok Choi Jongyoon Shin Jongho Kim Je-Soo Ko
Copyright Year	2009
Description	Author affiliation: Electronics and Telecommunications Research Institute (ETRI), Daejeon, 305-700, Republic of Korea (Jongyoon Shin; Jongho Kim; Je-Soo Ko) \|\| School of Information and Communication Engineering, Inha University, Incheon, 402-751, Republic of Korea (Sangho Yoon; Hanho Lee; Kihoon Lee; Chang-Seok Choi)
Abstract	This paper presents a high-speed Forward Error Correction (FEC) architecture based on the concatenated BCH code for 100-Gb/s optical communication systems. The concatenated BCH code consists of BCH(3860, 3824) and BCH(2040, 1930), which provides 7.98dB net coding gain at $10^{−12}$ corrected bit error rate without additive overhead as compared with the Reed-Solomon(255, 239) standardized in ITU-T G.975 and G.709. This architecture has been implemented with 90-nm CMOS standard cell technology in a supply voltage of 1.1V. The implementation results show that the concatenated BCH Super-FEC architecture can operates at a clock frequency of 400MHz and has a throughput of 102.4-Gb/s for 90-nm CMOS technology.
Starting Page	036
Ending Page	039
File Size	936251
Page Count	4
File Format	PDF
ISBN	9781424443352
ISSN	15206130
DOI	10.1109/SIPS.2009.5336245
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-07
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Concatenated codes Optical fiber communication CMOS technology Forward error correction Gain Bit error rate Reed-Solomon codes Voltage Clocks Frequency architecture Concatenated BCH code FEC
Content Type	Text
Resource Type	Article

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