NDLI: Design of an area efficient Reed-Solomon decoder ASIC chip

Content Provider	IEEE Xplore Digital Library
Author	Hyunman Chang Sunwoo, M.H.
Copyright Year	1999
Description	Author affiliation: Sch. of Electr. & Electron. Eng., Ajou Univ., Suwon, South Korea (Hyunman Chang)
Abstract	We describe an area efficient pipelined Reed-Solomon (RS) decoder. We propose two simple basic cell architectures which evaluate the error locator and the error magnitude polynomial in the general Euclid's algorithm. The evaluation involves high computational complexity, and thus, it affects the speed and the hardware complexity of RS decoders. The proposed architectures can reduce the hardware complexity by more than 16% of existing RS decoder architectures. The proposed RS decoder can be programmed to decode four RS codes defined in Galois field 2/sup 8/, i.e., (200, 188), (120, 108), (60, 48), and (40, 28) and can correct up to six errors. The fabricated FEC (Forward Error Correction) chip including the RS and Viterbi decoders operates at 40 MHz. The total number of gates for the RS decoder is about 31,000 and the FEC chip contains about 76,000 gates.
Starting Page	578
Ending Page	585
File Size	440148
Page Count	8
File Format	PDF
ISBN	0780356500
ISSN	15206130
DOI	10.1109/SIPS.1999.822364
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-10-22
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reed-Solomon codes Decoding Application specific integrated circuits Computer architecture Forward error correction Hardware Polynomials Computational complexity Galois fields Error correction codes
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 40-MHz encoder-decoder chip generated by a Reed-Solomon code compiler

An Architecture Of A High Speed Reed-Solomon Decoder

A Low-Complexity Reed-Solomon Decoder

Low complexity parallel Chien search architecture for RS decoder

A (208,192;8) Reed-Solomon decoder for DVD application

Design of a high performance Reed-Solomon decoder with switch box control logic [HDTV]

An area-efficient high-speed Reed-Solomon decoder in 0.25 /spl mu/m CMOS

Hardware implementation of the Reed-Solomon decoder

Architecture for a low complexity rate-adaptive Reed-Solomon encoder

Design of an area efficient Reed-Solomon decoder ASIC chip

Similar Documents

A 40-MHz encoder-decoder chip generated by a Reed-Solomon code compiler

An Architecture Of A High Speed Reed-Solomon Decoder

A Low-Complexity Reed-Solomon Decoder

Low complexity parallel Chien search architecture for RS decoder

A (208,192;8) Reed-Solomon decoder for DVD application

Design of a high performance Reed-Solomon decoder with switch box control logic [HDTV]

An area-efficient high-speed Reed-Solomon decoder in 0.25 /spl mu/m CMOS

Hardware implementation of the Reed-Solomon decoder

Architecture for a low complexity rate-adaptive Reed-Solomon encoder

Design of an area efficient Reed-Solomon decoder ASIC chip