NDLI: A 2 way VLIW processor architecture for embedded multimedia applications

Content Provider	IEEE Xplore Digital Library
Author	Jiyang Kang Jae-Woo Ahn Jiyoung Cho Ki-Il Kum Wonyong Sung
Copyright Year	1999
Description	Author affiliation: Sch. of Electr. Eng., Seoul Nat. Univ., South Korea (Jiyang Kang)
Abstract	As the complexity of multimedia applications increases, the need for efficient and compiler-friendly processor architectures also grows. In this paper, a new multimedia processor architecture is proposed. This processor has a 2-issue VLIW architecture with 64-bit SIMD arithmetic functional units to exploit the instruction-level and subword data parallelism found in multimedia applications. Moreover, densely encoded instructions supporting memory operands, DSP-like addressing modes, and SIMD capability boost the performance while keeping the code size and hardware cost small. To maximally utilize this architecture, a software environment including a code converter, a VLIW compiler system, and a compiled simulator has also been developed. The processor core has been synthesized for LSI logic 0.25 /spl mu/m library, which results in the total gate count of 102 K. In spite of the relatively smaller issue rate, the proposed processor shows a comparable or higher performance in terms of both the cycle count and the code size when compared to the 8-issue TMS320C62xx, for DSP benchmark kernels and an H.263 video encoder.
Starting Page	211
Ending Page	220
File Size	506623
Page Count	10
File Format	PDF
ISBN	0780356500
ISSN	15206130
DOI	10.1109/SIPS.1999.822326
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-10-22
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	VLIW Computer architecture Arithmetic Application software Hardware Costs Large scale integration Logic Software libraries Digital signal processing
Content Type	Text
Resource Type	Article

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