NDLI: A low power 3-D discrete wavelet transform processor for medical applications

Content Provider	IEEE Xplore Digital Library
Author	Badawy, W. Guoqing Zhang Talley, M. Weeks, M. Bayoumi, M.
Copyright Year	1999
Description	Author affiliation: Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA (Badawy, W.)
Abstract	This paper presents a low power 3-D discrete wavelet transform processor for medical applications. The main target of this work is the compression of Magnetic Resonance Imaging (MRI) data using a wavelet based scheme. A prototype has been developed to realize a 3-D wavelet compressor. The processor is based on an architecture that uses a centrally controlled unit to coordinate sub-systems which carry out the operations necessary for the data compression. The subsystems include a small cache memory used for block data storage, parallel high and low pass filters used for data calculation, and two coefficient units used to retrieve off-chip wavelet coefficients. The processor has been prototyped using 0.6 /spl mu/m CMOS (three metal) technology, the prototype processor is modular. It has been simulated at the functional, circuit, and physical levels. The performance measures of the prototype, area, time delay, power and utilization has been evaluated. The prototype operates at an estimated frequency of 272 MHz and dissipating 0.5 W of power.
Starting Page	65
Ending Page	74
File Size	689759
Page Count	10
File Format	PDF
ISBN	0780356500
ISSN	15206130
DOI	10.1109/SIPS.1999.822311
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-10-22
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete wavelet transforms Prototypes Magnetic resonance imaging CMOS technology Frequency estimation Biomedical imaging Medical services Biomedical equipment Centralized control Data compression
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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