NDLI: A core generator for fully synthesizable and highly parameterizable RISC-cores for system-on-chip designs

Content Provider	IEEE Xplore Digital Library
Author	Berekovic, M. Heistermann, D. Pirsch, P.
Copyright Year	1998
Description	Author affiliation: Hannover Univ., Germany (Berekovic, M.)
Abstract	Driven by the rapid advances in semiconductor technology the number of functional units that can be implemented on a single chip is rapidly increasing. This raises the need for programmable but small processor cores to handle control of operation as well as communication and synchronization between the different functional modules on the chip. We have developed a soft core generator for highly parameterizable RISC-cores. The instruction word width can be arbitrarily chosen between 8 and 32 bits. Independent of this, the data-path width can be selected between 8 and 64 bits respectively. DSP-like performance can be achieved with the instantiation of a 64-bit (splittable-) MAC-unit in the data-path. The number of registers is arbitrarily scalable. The resulting cores are generated in RTL-VHDL and are fully synthesizable. Worst-case timing simulation shows 100 MHz achievable clock-speed using a 3LM 0.5 /spl mu/m standard-cell technology. The size of the synthesized cores ranges from 900 gates for a multi-cycle 8 bit core to 10k gates for a 5-stage pipelined 32 bit core with 8 registers. Interfaces and behavioral models are provided for instruction and data memories as well as a runnable VHDL testbench with basic test patterns. As a result, a 16 bit RISC core with instruction and data memories can be implemented on 1 mm/sup 2/ of silicon area in a 0.35 /spl mu/m technology.
Starting Page	561
Ending Page	568
File Size	453239
Page Count	8
File Format	PDF
ISBN	0780349970
ISSN	15206130
DOI	10.1109/SIPS.1998.715818
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-10-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Communication system control Synchronization Timing Clocks Registers Reduced instruction set computing Silicon
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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