NDLI: Low-power GPS receiver design

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2015 IEEE Workshop on Signal Processing Systems (SiPS)

2014 IEEE Workshop on Signal Processing Systems (SiPS)

SiPS 2013 Proceedings

2012 IEEE Workshop on Signal Processing Systems

2011 IEEE Workshop on Signal Processing Systems (SiPS)

2010 IEEE Workshop On Signal Processing Systems

2009 IEEE Workshop on Signal Processing Systems

2008 IEEE Workshop on Signal Processing Systems

2007 IEEE Workshop on Signal Processing Systems

2006 IEEE Workshop on Signal Processing Systems Design and Implementation

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.

IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)

IEEE Workshop on Signal Processing Systems

2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)

2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528)

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)

Low-power GPS receiver design

Array signal processing for a wireless MEM sensor network

Study of cache system in video signal processors

Real-time software video encoder on a multimedia RISC processor

The MPEG-4 video coding standard-a VLSI point of view

Implementation of DCT-domain motion estimation and compensation

A system-on-chip design of a low-power smart vision system

Protecting ownership rights of a lossless image coder through hierarchical watermarking

Design and implementation of low-power DCT chip for portable multimedia terminals

A fixed-point multimedia DSP chip for portable multimedia services

A 16-bit parallel MAC architecture for a multimedia RISC processor

A heterogeneous HW-SW architecture for hand-held multimedia terminals

Re-evaluating MPEG motion compensation search criteria

A portable system for high-resolution digital image acquisition using wavelet image compression

Pentium-MMX-based implementation of a digital copier

Field programmable DSP transform arrays

An enhanced template matching algorithm and its chip implementation

On implementation and design of filter banks for subband adaptive systems

A flexible approach and VLSI architecture for computing discrete time-frequency distribution

A study about FPGA-based digital filters

Lossless compression of VQ indexes using search-order and correction codes

Multi-channel reverberation for computer music applications

An overlap-add free musical noise analysis-synthesis system

VLSI design and implementation of low-complexity adaptive turbo-code encoder and decoder for wireless mobile communication applications

Implementation of a DSSS modem ASIC chip for wireless LAN

Partitioning analog and digital processing in a single-chip GPS receiver

Reconfigurable signal processor for channel coding and decoding in low SNR wireless communications

Scheduling strategies for low-energy programmable digit-serial Reed-Solomon codecs

Rapid design of a single chip adaptive beamformer

A scalable VLSI architecture for multichannel blind deconvolution and source separation

Rapid design of high performance adaptive equalizer and Viterbi decoder for the class-IV PRML channel

Low-power equalizers for 51.84 Mb/s very-high-speed digital subscriber loop (VDSL) modems

Self-regulated GPS navigation processor

Low-complexity VLSI design and implementation of FFT-based multi-carrier direct sequence spread spectrum transceiver

A 1200 bits/s HSX speech coder for very-low-bit-rate communications

Computationally efficient fast algorithm and architecture for the IFFT/FFT in DMT/OFDM systems

Digital demodulator matching on a FPGA

Differential Kalman filtering for tracking Rayleigh fading channels

Blind channel and symbol estimation for wireless communications via an affinity neural network

Design and implementation of a nonlinear acoustic echo canceller

Multiport memory and floating point Cordic pipeline in Jacobium processing elements

High-speed VLSI state-space orthogonal IIR digital filters using matrix lookahead

A block-floating-point system for multiple datapath DSP

Reusable cryptographic VLSI core based on the SAFER K-128 algorithm with 251.8 Mbit/s throughput

RNS scaling based on pipelined multipliers for prime moduli

Digit-serial reconfigurable FPGA logic block architecture

Compactly merged arithmetic for wavelet transforms

Using DG2VHDL to synthesize an FPGA implementation of the 1-D discrete wavelet transform

Arbitration schemes synthesis approach for multiprocessor systems

Design and implementation of the Almanet environment

A study of loop unrolling for VLIW-based DSP processors

A uniform analysis method for DSP architectures and instruction sets with a comprehensive example

A performance evaluation of a RISC-based digital signal processor architecture

A system-level reuse methodology for embedded data-dominated applications

A core generator for fully synthesizable and highly parameterizable RISC-cores for system-on-chip designs

Word-length optimization for high-level synthesis of digital signal processing systems

Loop scheduling algorithm for timing and memory operation minimization with register constraint

Loop Scheduling Algorithm For Timing And Memory Operation Minimization With Register Constraint

Optimized software synthesis for digital signal processing algorithms: an evolutionary approach

Input recoding for reducing power in distributed arithmetic

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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