NDLI: An efficient VLSI architecture of sub-pixel interpolator for AVS encoder

Content Provider	IEEE Xplore Digital Library
Author	Chen Guanghua Zhang xiaoli Liu Ming Zhu Jingming Ma Shiwei Zeng Weimin
Copyright Year	2008
Description	Author affiliation: Minist. of Educ. & Microelectron. Res. & Dev. Center, Shanghai Univ., Shanghai (Chen Guanghua; Zhang xiaoli; Liu Ming; Zhu Jingming; Ma Shiwei; Zeng Weimin)
Abstract	Interpolation is the main bottleneck in AVS real-time high definition video encoder for its high memory bandwidth and large calculation complexity caused by the new coding features of variable block size and 4-tap filter. In this paper, an efficient VLSI architecture of interpolation supporting AVS Baseline@L4 is presented. Vertical redundant data reuse, horizontal redundant data reuse and sub-pixel data reuse schemes are presented to reduce memory bandwidth and processing cycle. The separated 1-D interpolation filters are used to improve throughput and hardware utilization. The proposed design is implemented on the Vertex4 XC4VLX200 field programmable gate array with operating frequency of 150 MHz and can support 1080p (1920 times 1080) 30 fps AVS real-time encoder. It is a useful intellectual property design for real-time high definition video application.
Starting Page	1255
Ending Page	1258
File Size	107770
Page Count	4
File Format	PDF
ISBN	9781424421787
DOI	10.1109/ICOSP.2008.4697359
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-26
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Interpolation High definition video Bandwidth Filters Throughput Hardware Field programmable gate arrays Frequency Intellectual property separated 1-D architecture AVS interpolation data reuse
Content Type	Text
Resource Type	Article

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