NDLI: ARM7 compatible 32-bit RISC processor design and verification

Content Provider	IEEE Xplore Digital Library
Author	Geun-young Jeong Ju-sung Park Hyun-woo Jo Byung-woo Yoon Myung-jin Lee
Copyright Year	2005
Description	Author affiliation: Samsung SDI, South Korea (Geun-young Jeong)
Abstract	The design and verification of a 32-bit general-purpose microprocessor, which is compatible with ARM7 RISC core, is described. In the architectural point of view, the processor has 3-stage pipeline, 6 register banks, 32-bit ALU, and 4-cycle MAC. The core described here was designed by latch base for low power and low complexity. Its functional operation was verified by comparison the results of logic simulation with those of the commercial simulator. Each instruction and its random combinations were tested. The designed core was emulated to check its proper operation for various applications, such as ADPCM, SOLA (voice speed variation), MP3 decoding. Finally it was implemented in 0.5/spl mu/m CMOS process and it carried out successfully those algorithms.
Starting Page	607
Ending Page	610
File Size	674296
Page Count	4
File Format	PDF
ISBN	0780389433
DOI	10.1109/KORUS.2005.1507795
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-26
Publisher Place	Russia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reduced instruction set computing Process design Microprocessors Pipelines Registers CMOS logic circuits Testing Digital audio players Decoding CMOS process
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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