NDLI: Top-down design for 32-bit RISC core

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Top-down design for 32-bit RISC core

Content Provider	IEEE Xplore Digital Library
Author	Xu Zhongyou Liu Honaxin Chou Changsheng Yang Xiaoli Dai Lu Xu Jingjing Chi Li
Copyright Year	1996
Description	Author affiliation: Northeast Microelectron. Inst., Shenyang, China (Xu Zhongyou)
Abstract	This paper is to introduce the 32-bit RISC IU chip LC47811. It was designed and fabricated in China last year. It is designed as the core of embedded microcontrollers for future applications. The design of RISC chip started at RTL level with Top-Down methodology in June 1995, we generated the gate-level net-list by logic synthesis and complete the layout by automatic place and route on COMPASS in Sept. 1995. We finished all design, process, wafer test, bonding, packaging and final test in China by May 1996. This design is proved successful for the first time.
Starting Page	104
Ending Page	106
File Size	232983
Page Count	3
File Format	PDF
ISBN	7543909405
DOI	10.1109/ICASIC.1996.562762
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-10-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reduced instruction set computing CMOS logic circuits CMOS process Registers Logic design Sun Large scale integration Testing Licenses Microelectronics
Content Type	Text
Resource Type	Article

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