NDLI: GP based transistor sizing for optimal design of nanoscale CMOS inverter

Content Provider	IEEE Xplore Digital Library
Author	Pattanaik, M. Banerjee, S. Bahinipati, B.K.
Copyright Year	2003
Description	Author affiliation: Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, India (Pattanaik, M.; Banerjee, S.)
Abstract	This paper proposes a simple method to formulate the transistor sizing problem as a geometric program (GP) by using a modified I-V model which performs well up to 10 nm. The geometric program model for dynamic power delay product (PDP) expression has been formulated by using the modified I-V model for nanoscale CMOS inverter. The model has been solved efficiently, which generates a number of important practical consequences. This method computes the absolute limit of performance for given input frequency and load capacitance of a transistor and technology parameters. The accuracy of performance prediction in the transistor-sizing (through geometric programming) problem is verified due to its closeness to SPICE simulation (250 nm) results. Further the approach has been extended to predict the transistor sizing for nanoscale (up to 50 nm) CMOS inverter and the simulation results of the proposed model are compared with the Berkeley Predictive Technology Model (BPTM) to establish the usefulness of the approach.
Sponsorship	IEEE Nanotechnol. Council IEEE Region 6 Western USA
Starting Page	524
Ending Page	527
File Size	251380
Page Count	4
File Format	PDF
ISBN	0780379764
DOI	10.1109/NANO.2003.1230962
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-08-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Inverters Semiconductor device modeling Solid modeling Predictive models CMOS technology Delay Frequency Capacitance Accuracy SPICE
Content Type	Text
Resource Type	Article

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