NDLI: Design of a scalable digital Wireless Channel Emulator for networking radios

Content Provider	IEEE Xplore Digital Library
Author	Buscemi, S. Sass, R.
Copyright Year	2011
Description	Author affiliation: Reconfigurable Computing Systems Lab, Univ. of North Carolina at Charlotte, USA (Sass, R.) \|\| Advanced Communication Technologies Lab, SPAWAR Systems Center Atlantic, Charleston, South Carolina, USA (Buscemi, S.)
Abstract	The utilization of digital Wireless Channel Emulators (WCE) with networking radios is hampered by the inability to efficiently scale a digital WCE to a large number of nodes. While analog WCEs are capable of large numbers of nodes they cannot cost effectively emulate channel effects such as fading and multipath which significantly limits the accuracy and flexibility of the emulation. If such a large scale digital WCE were to exist, a significant amount of time and money could be saved by testing networking radios in a laboratory before running lengthily and costly field tests. By utilizing the repeatability of a laboratory environment it will be possible to investigate and solve issues more quickly and efficiently. This will enable the performance of the radios to be known with a high degree of certainty before they are brought to the field. This paper describes research into scalability of digital wireless channel emulators highlighting technical challenges and presents a design solution that will meet the needs of current and future networking radio system testing. The major design challenges of the system include: computational and network capability, end-to-end propagation delay, and accuracy of the emulation. A solution to these issues involves the creation of an FPGA computational cluster networked via high speed transceivers and a signal path design that utilizes hardware resources effectively. A prototype was developed using this signal path design and COTS hardware to explore each of the challenges and to take metrics demonstrating the capability of a full scale system to meet these challenges. Additionally, this prototype was connected to Joint Tactical Radio Systems (JTRS) radios to demonstrate the capabilities of the system with military hardware.
Starting Page	1858
Ending Page	1863
File Size	371069
Page Count	6
File Format	PDF
ISBN	9781467300797
ISSN	21557578
e-ISBN	9781467300810
DOI	10.1109/MILCOM.2011.6127583
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Delay Hardware Prototypes Bandwidth Equations Clocks
Content Type	Text
Resource Type	Article

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