NDLI: Delay/overhead measurements for circuit-emulation tunnels

Content Provider	IEEE Xplore Digital Library
Author	Etefia, B. Hant, J.
Copyright Year	2011
Description	Author affiliation: The Aerospace Corporation, P.O. Box 92957, Los Angeles, CA 90009-2957, USA (Etefia, B.; Hant, J.)
Abstract	Due to unique security and communication channel constraints, military communication networks often must send data between serial devices at extremely low data rates. As military networks begin to migrate towards packet-based transport, data from these serial applications will need to be packetized and transferred from sender to receiver in a circuit-emulation tunnel. In addition to packetizing and serializing the data sent across the network, these circuit-emulation tunnels must also remove the jitter caused by packet-based transport. Packetizing/serializing data and removing jitter can result in a significant amount of bandwidth overhead and delay. This paper provides a brief description of various circuit-emulation technologies and a detailed analysis of the bandwidth overhead and delay due to serial-to-packet conversion. An analytical model was developed that predicts bandwidth overhead and delays resulting from the circuit-emulation tunnel as a function of the serial interface speed, packet size, jitter buffering, and control messaging. The analytical model was tested against a series of network emulation experiments using commercial circuit-to-packet devices. Results show a fundamental trade between bandwidth overhead and delay. Circuit-emulation tunnels with small packet sizes have short packetization delays and large bandwidth overhead, while tunnels with large packet sizes have long packetization delays and smaller bandwidth overhead. These trends are more pronounced at the lower data rates because it takes a longer time for the serial data to be packetized. Experimental and theoretical results presented in this paper show similar trends with slight discrepancies due to internal processing effects not included in the analytical model.
Starting Page	1684
Ending Page	1689
File Size	1641088
Page Count	6
File Format	PDF
ISBN	9781467300797
ISSN	21557578
e-ISBN	9781467300810
DOI	10.1109/MILCOM.2011.6127552
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Bandwidth Emulation Jitter Time division multiplexing Integrated circuit modeling Mathematical model Circuit-Emulation
Content Type	Text
Resource Type	Article

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