NDLI: High-Q RF inductors on standard silicon realized using wafer-level packaging techniques

Content Provider	IEEE Xplore Digital Library
Author	Carchon, G. Jenei, S. Carbonell, L. Van Hove, M. Decoutere, S. De Raedt, W. Maex, K. Beyne, E.
Copyright Year	2003
Description	Author affiliation: IMEC, Heverlee, Belgium (Carchon, G.; Jenei, S.; Carbonell, L.; Van Hove, M.; Decoutere, S.; De Raedt, W.; Maex, K.; Beyne, E.)
Abstract	Wafer level packaging (WLP) techniques have been used to integrate state of the art high Q on-chip inductors on top of a five-levels-of-metal (5LM) Cu damascene back-end of line (BEOL) silicon process using 20 /spl Omega/.cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric (BCB) and Cu layers. For a BCB/Cu-thickness of 16 /spl mu/m/10 /spl mu/m, a peak Q-factor of 34 at 4.3 GHz has been obtained for a 1 nH inductor (substrate contacts present at both ports) with a resonance frequency of 29 GHz; the Q-factor further tops 30 over the 2.1-5.4 GHz frequency range. If a substrate contact is present at only 1 port, Q/sub max/ increases to 38 at 4.7 GHz. Patterned polysilicon ground shields further improve this performance: a Q-factor increase of 90% is demonstrated at 7 GHz for a 2.25 nH inductor. A good agreement between measurements and 3-D simulations is demonstrated.
Starting Page	1287
Ending Page	1290
File Size	311665
Page Count	4
File Format	PDF
ISBN	0780376951
ISSN	0149645X
DOI	10.1109/MWSYM.2003.1212605
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-06-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Radio frequency Silicon Wafer scale integration Passivation Q factor Dielectric substrates Thin film inductors Metallization Spirals Dielectric losses
Content Type	Text
Resource Type	Article
Subject	Condensed Matter Physics Electrical and Electronic Engineering Radiation

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in