NDLI: Understanding correlated drain and gate current fluctuations

Content Provider	IEEE Xplore Digital Library
Author	Goes, W. Toledano-Luque, M. Baumgartner, O. Bina, M. Schanovsky, F. Kaczer, B. Grasser, T.
Copyright Year	2013
Description	Author affiliation: imec, Leuven, Belgium (Toledano-Luque, M.; Kaczer, B.) \|\| Inst. for Microelectron., Tech. Univ. Wien, Vienna, Austria (Goes, W.; Baumgartner, O.; Bina, M.; Schanovsky, F.; Grasser, T.)
Abstract	Recently, some experimental groups have observed the occurrence of correlated drain and gate current fluctuations, which indicate that both currents are influenced by the charge state of the same defect. Since the physical reason behind this phenomenon is unclear at the moment, we evaluated two different explanations: The first model assumes that direct tunneling of carriers is affected by the electrostatic field of the charged defect. Interestingly, this model inherently predicts the gate bias and temperature dependences observed in the experiments and is therefore quite promising at a first glance. In the second model, our multi-state defect model is employed to describe trap-assisted tunneling as a combination of two consecutive nonradiative multi-phonon transitions - namely hole capture from the substrate followed by hole emission into the poly-gate. The latter transition is found to be in the weak electron-phonon coupling regime, which requires the consideration of all band states instead of only the band edges. Our investigation shows that the electrostatic model must be discarded since it predicts only small changes in the gate current while the extended variant of the multi-state defect model delivers quite promising results.
Starting Page	51
Ending Page	56
File Size	433533
Page Count	6
File Format	PDF
ISBN	9781479912414
ISSN	19461550
e-ISBN	9781479904808
DOI	10.1109/IPFA.2013.6599125
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-07-15
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Substrates Tunneling Noise Electrostatics Couplings Electron traps
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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