NDLI: Failure analysis from the back side of a die

Content Provider	IEEE Xplore Digital Library
Author	Liebert, S.
Copyright Year	2001
Description	Author affiliation: Philips Semicond., Zurich, Switzerland (Liebert, S.)
Abstract	Reproducible back side sample preparation and failure analysis methods becomes increasingly important due to the increasing number of metal levels within semiconductor devices and the ongoing transition to new packages like flip-chip or lead-on-chip. Defects are often located in the lowest chip levels, which make front side electrical defect localization very difficult. Otherwise electrical defect localization in flip-chip and lead-on-chip devices is only possible from the die back side. We developed a failure analysis flow for these die types which contains back side and front side failure analysis methods, consisting of back side photoemission microscopy after bulk Si thinning and electrical recontacting of the die for electrical defect localization. From the type of stress test, test results and fault location, the defect type can often be deduced. With junction leakage, latch up or Al spiking, the die should be prepared for front side analysis, since during further back side preparation, the whole die active area is removed. Gate oxide defects, particles and interrupted conductive interconnects can be analyzed from both the front and back sides of the die. Due to die fragility after bulk Si thinning for electrical defect localization, defect preparation becomes much easier from the back side. After bulk Si removal, optical inspection is possible. Particles or, for example, damage caused by electrostatic overstress might be visible. Gate oxide defects are analyzable by SEM and interrupted conductive interconnects are detectable using passive voltage contrast or electrical probing with AFM.
Sponsorship	IEEE Electron Device Soc
Starting Page	187
Ending Page	194
File Size	1889587
Page Count	8
File Format	PDF
ISBN	0780366751
DOI	10.1109/IPFA.2001.941484
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-07-13
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Failure analysis Scanning electron microscopy Testing Semiconductor devices Semiconductor device packaging Lead compounds Photoelectricity Atomic force microscopy Stress Fault location
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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