NDLI: Exploring speculative parallelism in SPEC2006

Content Provider	IEEE Xplore Digital Library
Author	Packirisamy, V. Zhai, A. Wei-Chung Hsu Pen-Chung Yew Tin-Fook Ngai
Copyright Year	2009
Description	Author affiliation: University of Minnesota, Minneapolis, USA (Packirisamy, V.; Zhai, A.; Wei-Chung Hsu; Pen-Chung Yew) \|\| Intel Corporation, USA (Tin-Fook Ngai)
Abstract	The computer industry has adopted multi-threaded and multi-core architectures as the clock rate increase stalled in early 2000's. It was hoped that the continuous improvement of single-program performance could be achieved through these architectures. However, traditional parallelizing compilers often fail to effectively parallelize general-purpose applications which typically have complex control flow and excessive pointer usage. Recently hardware techniques such as Transactional Memory (TM) and Thread-Level Speculation (TLS) have been proposed to simplify the task of parallelization by using speculative threads. Potential of speculative parallelism in general-purpose applications like SPEC CPU 2000 have been well studied and shown to be moderately successful. Preliminary work examining the potential parallelism in SPEC2006 deployed parallel threads with a restrictive TLS execution model and limited compiler support, and thus only showed limited performance potential. In this paper, we first analyze the cross-iteration dependence behavior of SPEC 2006 benchmarks and show that more parallelism potential is available in SPEC 2006 benchmarks, comparing to SPEC2000. We further use a state-of-the-art profile-driven TLS compiler to identify loops that can be speculatively parallelized. Overall, we found that with optimal loop selection we can potentially achieve an average speedup of 60% on four cores over what could be achieved by a traditional parallelizing compiler such as Intel's ICC compiler.We also found that an additional 11% improvement can be potentially obtained on selected benchmarks using 8 cores when we extend TLS on multiple loop levels as opposed to restricting to a single loop level.
Starting Page	77
Ending Page	88
File Size	1387299
Page Count	12
File Format	PDF
ISBN	9781424441846
DOI	10.1109/ISPASS.2009.4919640
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parallel processing Computer architecture Yarn Computer industry Clocks Continuous improvement Application software Hardware
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Exploiting loop-level parallelism with the Shift Architecture

Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications

Exploring speculative parallelism in spec2006.

In search of speculative thread-level parallelism

Loop-level Speculative Parallelism in Embedded Applications

Exploring Speculative Parallelism in SPEC2006

Hybrid Parallelism for XML SAX Parsing

Experiences using the Cray Multi-Threaded Architecture (MTA-2)

Reverse Compilation for Speculative Parallel Threading

Exploring speculative parallelism in SPEC2006

Similar Documents

Exploiting loop-level parallelism with the Shift Architecture

Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications

Exploring speculative parallelism in spec2006.

In search of speculative thread-level parallelism

Loop-level Speculative Parallelism in Embedded Applications

Exploring Speculative Parallelism in SPEC2006

Hybrid Parallelism for XML SAX Parsing

Experiences using the Cray Multi-Threaded Architecture (MTA-2)

Reverse Compilation for Speculative Parallel Threading

Exploring speculative parallelism in SPEC2006