NDLI: Zesto: A cycle-level simulator for highly detailed microarchitecture exploration

Content Provider	IEEE Xplore Digital Library
Author	Loh, G.H. Subramaniam, S. Yuejian Xie
Copyright Year	2009
Description	Author affiliation: Georgia Institute of Technology, College of Computing, USA (Loh, G.H.; Subramaniam, S.; Yuejian Xie)
Abstract	For academic computer architecture research, a large number of publicly available simulators make use of relatively simple abstractions for the microarchitecture of the processor pipeline. For some types of studies, such as those for multi-core cache coherence designs, a simple pipeline model may suffice. For detailed microarchitecture research, such as those that are sensitive to the exact behavior of out-of-order scheduling, ALU and bypass network contention, and resource management (e.g., RS and ROB entries), an over-simplified model is not representative of modern processor organizations. We present a new timing simulator that models a modern x86 microarchitecture at a very low level, including out-of-order scheduling and execution that much more closely mirrors current implementations, a detailed cache/memory hierarchy, as well as many x86-specific microarchitecture features (e.g., simple vs. complex decoders, micro-op decomposition and fusion, microcode lookup overhead for long/complex x86 instructions).
Starting Page	53
Ending Page	64
File Size	231104
Page Count	12
File Format	PDF
ISBN	9781424441846
DOI	10.1109/ISPASS.2009.4919638
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microarchitecture Computational modeling Pipelines Out of order Processor scheduling Computer architecture Computer simulation Coherence Resource management Timing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Zesto: A Cycle-Level Simulator for Highly Detailed Microarchitecture Exploration (2009)

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Design and implementation of a high speed microprocessor simulator BurstScalar

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Validation of Turandot, a fast processor model for microarchitecture exploration

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Zesto: A cycle-level simulator for highly detailed microarchitecture exploration

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Zesto: A Cycle-Level Simulator for Highly Detailed Microarchitecture Exploration (2009)

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Zesto: A cycle-level simulator for highly detailed microarchitecture exploration