NDLI: Analytical Energy Models for MPI Communications on a Sandy-Bridge Architecture

Content Provider	IEEE Xplore Digital Library
Author	Almeida, F. Blanco, V. Gonzalez, I. Cabrera, A. Gimenez, D.
Copyright Year	2013
Description	Author affiliation: Inst. Tecnol. y de Energias Renovables, Santa Cruz de Tenerife, Spain (Cabrera, A.) \|\| Dept. Estadistica, I.O. y Comput., Univ. de La Laguna, La Laguna, Spain (Almeida, F.; Blanco, V.; Gonzalez, I.) \|\| SCPP Group, Univ. de Murcia, Murcia, Spain (Gimenez, D.)
Abstract	Complexity in parallel computation for current HPC systems has being modeled in order to estimate time and energy consumption, which have been conduced to evaluate real costs. Communication analytical models for time and energy comsumption are an attractive issue as part of this cost analysis in parallel computation. In this paper, we present time and energy analytical models for MPI communications using OSU micro benchmarks under Sandy Bridge-EP computer architecture. RAPL (Running Average Power Limit) interface has been setup to provide mechanisms to enforce real energy consumption measurements for OSU micro benchmarks on this architecture. Our applied methodology defines an experimental framework based on several core configurations and different transmission rates. The RAPL interface allows us to obtain different energy values for the OSU benchmark executions. The measures obtained are used to obtain time and energy consumption parameters of our models, establishing average errors below 1% for almost all configurations in real executions under this computer architecture for an ad-hoc model. Alternative and simpler time and energy models are also proposed with errors up to 3.1% for the worst case.
Starting Page	868
Ending Page	876
File Size	595315
Page Count	9
File Format	PDF
ISBN	9780769551173
ISSN	01903918
DOI	10.1109/ICPP.2013.103
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-01
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sockets Computational modeling Analytical models Energy measurement Current measurement Microarchitecture Hardware Multicore systems Energy-efficent algorithms Energy models MPI communications
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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