NDLI: Exposing ILP in custom hardware with a dataflow compiler IR

Content Provider	IEEE Xplore Digital Library
Author	Zaidi, A.M.
Copyright Year	2013
Description	Author affiliation: Comput. Lab., Univ. of Cambridge, Cambridge, UK (Zaidi, A.M.)
Abstract	With the impending Dark Silicon problem spelling doom for multicore performance scaling, there is an ever increasing need for processor architectures with much better energy efficiency. To address this, designers are increasingly utilising custom (and reconfigurable) computing to provide orders-of-magnitude improvements in energy efficiency over equivalent software implementations of the same code. Unfortunately, one of the key issues with custom computing is that it is often unable to match the performance of conventional processors when implementing irregular code with complex control-flow. Out-of-order superscalar processors implement aggressive branch prediction to speculate across multiple branches with very high accuracy, dynamically exposing ILP. But custom hardware lacks an efficient and safe control-flow speculation mechanism (particularly for loops), as it is difficult to implement misprediction roll-back and recovery in hardware without introducing a centralized synchronization bottleneck. By providing a mechanism for compiling high level languages to hardware, as well as improving performance of control-flow intensive code in hardware, much more pervasive utilization of custom and reconfigurable hardware were enable for general-purpose computation, thereby helping to mitigate the effects of dark silicon.
Starting Page	411
Ending Page	411
File Size	269564
Page Count	1
File Format	PDF
ISBN	9781479910182
ISSN	1089795X
e-ISBN	9781479910212
DOI	10.1109/PACT.2013.6618841
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-07
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Computer architecture Silicon Parallel processing Dynamic scheduling Field programmable gate arrays Computers Instruction Level Parallelism Dark Silicon Dataflow High-level Synthesis
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Hardware and Architecture Software

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