NDLI: Store-ordered streaming of shared memory

Content Provider	IEEE Xplore Digital Library
Author	Wenisch, T.F. Somogyi, S. Hardavellas, N. Jangwoo Kim Gniady, C. Ailamaki, A. Falsafi, B.
Copyright Year	2005
Description	Author affiliation: Comput. Archit. Lab., Carnegie Mellon Univ., Pittsburg, PA, USA (Wenisch, T.F.; Somogyi, S.; Hardavellas, N.; Jangwoo Kim)
Abstract	Coherence misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. Memory streaming provides a promising solution to the coherence miss bottleneck because it improves memory level parallelism and lookahead while using on-chip resources efficiently. We observe that the order in which shared data are consumed by one processor is correlated to the order in which they were produced by another. We investigate this phenomenon and demonstrate that it can be exploited to send store-ordered streams (SORDS) of shared data from producers to consumers, thereby eliminating coherent read misses. Using a trace-driven analysis of all user and OS memory references in a cache-coherent distributed shared-memory multiprocessor, we show that SORDS-based memory streaming can eliminate between 36% and 100% of all coherent read misses in scientific workloads and between 23% and 48% in online transaction processing workloads.
Starting Page	75
Ending Page	84
File Size	326545
Page Count	10
File Format	PDF
ISBN	076952429X
ISSN	1089795X
DOI	10.1109/PACT.2005.37
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-09-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Data structures Transistors Fabrication Technological innovation Chip scale packaging Communication switching Memory architecture Out of order History
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Hardware and Architecture Software

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