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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chandramouli, B. Carter, J.B. Hsieh, W.C. McKee, S.A. |
| Copyright Year | 2001 |
| Description | Author affiliation: Sch. of Comput., Utah Univ., Salt Lake City, UT, USA (Chandramouli, B.) |
| Abstract | Loop transformations and array restructuring optimizations usually improve performance by increasing the memory locality of applications, but not always. For instance, loop and array restructuring can either complement or compete with one another. Previous research has proposed integrating loop and array restructuring, but there existed no analytic framework for determining how best to combine the optimizations for a given program. Since the choice of which optimizations to apply, alone or in combination, is highly application and input-dependent, a cost framework is needed if integrated restructuring is to be automated by an optimizing compiler. To this end, we develop a cost model that considers standard loop optimizations along with two potential forms of array restructuring: conventional copying-based restructuring and remapping-based restructuring that exploits a smart memory controller. We simulate eight applications on a variety of input sizes and with a variety of hand-applied restructuring optimizations. We find that employing a fixed strategy does not always deliver the best performance. Finally; our cost model accurately predicts the best combination of restructuring optimizations among those we examine, and yields performance within a geometric mean of 5% of the best combination across all benchmarks and input sizes. |
| Starting Page | 131 |
| Ending Page | 140 |
| File Size | 999422 |
| Page Count | 10 |
| File Format | |
| ISBN | 0769513638 |
| ISSN | 1089796X |
| DOI | 10.1109/PACT.2001.953294 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-09-08 |
| Publisher Place | Spain |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Cost function Optimizing compilers Hardware Delay Application software Automatic control Size control Predictive models Software performance Bandwidth |
| Content Type | Text |
| Resource Type | Article |
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