NDLI: CAR: Securing PCM Main Memory System with Cache Address Remapping

Content Provider	IEEE Xplore Digital Library
Author	Gang Wu Huxing Zhang Yaozu Dong Jingtong Hu
Copyright Year	2012
Abstract	Phase Change Memory (PCM) has emerged as a promising alternative of DRAM to provide energy-efficient and high-capacity memory for high performance servers. A new DRAM + PCM hybrid memory architecture has been proposed to leverage PCM's high density and DRAM's robustness and performance. One of the big challenges of PCM is its limited write endurance (10^7 ~ 10^8 times per cell). By knowing the association between DRAM and PCM, malicious software can easily force DRAM cache to be flushed continuously, which produces writes to certain PCM cells repeatedly (known as selective attack) and wears out PCM. Although existing wear-leveling approaches could evenly distribute writes under selective attack, the overall endurance of PCM is still severely impacted, and therefore it is suboptimal. In this paper, we propose Cache Address Remapping (CAR), that can adaptively remap DRAM cache address, to hide the association between DRAM and PCM. Moreover, CAR can minimize the write-back traffic to PCM under selective attack by uniformly distributing the writes to a single cache set into different cache sets. We propose a practical and low overhead implementation of CAR, called RanCAR. Experimental results show that CAR could reduce DRAM cache miss rate by ~4600x under selective attack, and prolong PCM lifetime from several minutes to 13.8 years on average.
Starting Page	628
Ending Page	635
File Size	530231
Page Count	8
File Format	PDF
ISBN	9781467345651
ISSN	15219097
e-ISBN	9780769549033
DOI	10.1109/ICPADS.2012.90
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-17
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase change materials Random access memory Indexes Computer architecture Microprocessors Servers Hardware Malicious Attack Phase Change Memory Address Remapping Endurance Hybrid Memory System
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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