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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Koester, M. Porrmann, M. Ruckert, U. |
| Copyright Year | 2005 |
| Description | Author affiliation: Heinz Nixdorf Inst., Paderborn Univ., Germany (Koester, M.; Porrmann, M.; Ruckert, U.) |
| Abstract | Dynamic reconfiguration is a promising approach for resource efficient utilization of microelectronic systems. However, work on general approaches to model reconfigurable hardware is quite rare. Therefore, we have developed a new analytical model, which can be used for the analysis of the various approaches to dynamic reconfiguration. Based on our model we define metrics for partial reconfiguration to evaluate different system approaches. Our main objective is to analyze placement algorithms for partially reconfigurable architectures. The model is able to consider miscellaneous constraints and cost parameters for online placement. Thus, placement can be adapted to dynamically changing system environments. |
| Sponsorship | IEEE Comput. Soc. Tech. Comm. on Parallel Process |
| File Size | 113891 |
| File Format | |
| ISBN | 0769523129 |
| DOI | 10.1109/IPDPS.2005.343 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-04-04 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Reconfigurable architectures Field programmable gate arrays Hardware Analytical models Computer architecture Circuits Microelectronics Algorithm design and analysis Costs Educational institutions |
| Content Type | Text |
| Resource Type | Article |
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