NDLI: Simultaneous wire permutation, inversion, and spacing with genetic algorithm for energy-efficient bus design

Content Provider	IEEE Xplore Digital Library
Author	Shanq-Jang Ruan Naroska, E. Schwiegelshohn, U.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan (Shanq-Jang Ruan)
Abstract	With decreasing feature size on silicon, the coupling capacitances of buses grow rapidly causing a significant impact on the power consumption of the whole chip. Thus, buses should be designed and optimized to dissipate less power without sacrificing performance. In this paper, we address this problem by simultaneously optimizing wire permutation, inversion and spacing (space between consecutive wires) using a combination of optimal as well as genetic algorithms. Unlike previous studies, our approach is applicable to not only address buses (behave more regularly), but also instruction buses of microprocessors. For the spacing problem, an algorithm is presented which determines the optimal solution instead of applying time consuming heuristic algorithms as presented in (L. Macchiarulo et al., 2002). For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs. We simulate different combinations among permutation, spacing, and inversion. Integrated all optimization techniques together, our approach can save energy up to 68% for the best case and 58% on average while only increasing the total wire space by about 50% (compared to a bus with minimal spacing between adjacent wires for a particular technology).
Sponsorship	IEEE Comput. Soc. Tech. Comm. on Parallel Process
File Size	395197
File Format	PDF
ISBN	0769523129
DOI	10.1109/IPDPS.2005.403
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-04-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wire Genetic algorithms Energy efficiency Algorithm design and analysis Space technology Silicon Capacitance Energy consumption Design optimization Microprocessors
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in